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| ds07-16305-2e fujitsu semiconductor data sheet 32-bit risc microcontroller cmos fr series MB91107/108 MB91107/108 n description the MB91107 is a standard single-chip microcontroller constructed around the 32-bit risc cpu (fr* family) core with abundant i/o resources and bus control functions optimized for high-performance/high-speed cpu processing for embedded controller applications. to support the vast memory space accessed by the 32-bit cpu, the MB91107 normally operates in the external bus access mode and executes instructions on the internal 1 kbyte cache memory and ram (MB91107: 128 kbytes, mb91108: 160 kbytes) for enhanced performance. the MB91107 is optimized for applications requiring high-performance cpu processing such as navigation sys- tems, high-performance faxs and printer controllers. *: fr family stands for fujitsu risc controller. n features fr cpu ? 32-bit risc, load/store architecture, 5-stage pipeline ? operating clock frequency: internal 50 mhz/external 25 mhz (pll used at source oscillation 12.5 mhz) ? general purpose registers: 32 bits 16 ? 16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle ? memory to memory transfer, bit processing, barrel shifter processing: optimized for embedded applications ? function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems supporting high level languages (continued) n pac k ag e 120-pin plastic lqfp (fpt-120p-m21)
MB91107/108 2 (continued) ? register interlock functions, efficient assembly language coding ? branch instructions with delay slots: reduced overhead time in branch executions ? internal multiplier/supported at instruction level signed 32-bit multiplication: 5 cycles signed 16-bit multiplication: 3 cycles ? interrupt (push pc and ps): 6 cycles, 16 priority levels bus interface ? clock doubler: internal 50 mhz, external bus 25 mhz operation ? 25-bit address bus (32 mbytes memory space) ? 8/16-bit data bus ? basic external bus cycle: 2 clock cycles ? chip select outputs for setting down to a minimum memory block size of 64 kbytes: 8 ? interface supported for various memory technologies dram interface (area 4 and 5) ? automatic wait cycle insertion: flexible setting, from 0 to 7 for each area ? unused data/address pins can be configured us input/output ports ? little endian mode supported (select 1 area from area 1 to 5) dram interface ? 2 banks independent control (area 4 and 5) ? double cas dram (normal dram i/f) / single cas dram / hyper dram ? basic bus cycle: normally 5 cycles, 2-cycle access possible in high-speed page mode ? programmable waveform: automatic 1-cycle wait insertion to ras and cas cycles ?dram refresh cbr refresh (interval time configurable by 6-bit timer) self-refresh mode ? supports 8/9/10/12-bit column address width ? 2cas/1we, 2we/1cas selective cache memory ? 1-kbyte instruction cache memory ? 2 way set associative ? 32 block/way, 4 entry(4 word)/block ? lock function: for specific program code to be resident in cache memory dmac (dma controller) ? 8 channels ? transfer incident/external pins/internal resource interrupt requests ? transfer sequence: step transfer/block transfer/burst transfer/continuous transfer ? transfer data length: 8 bits/16 bits/32 bits selective ? nmi/interrupt request enables temporary stop operation uart ? 3 independent channels ? full-duplex double buffer ? data length: 7 bits to 9 bits (non-parity), 6 bits to 8 bits (parity) ? asynchronous (start-stop system), clk-synchronized communication selective ? multi-processor mode ? internal 16-bit timer (u-timer) operating as a proprietary baud rate generator: generates any given baud rate (continued) MB91107/108 3 (continued) ? use external clock can be used as a transfer clock ? error detection: parity, frame, overrun 10-bit a/d converter (successive approximation conversion type) ? 10-bit resolution, 4 channels ? successive approximation type: conversion time of 5.6 m s at 25 mhz ? internal sample and hold circuit ? conversion mode: single conversion/scanning conversion/repeated conversion selective ? start: software/external trigger/internal timer selective 16-bit reload timer ? 16-bit timer: 3 channels ? internal clock: 2 clock cycle resolution, divide by 2/8/32 selective other interval timers ? 16-bit timer: 3 channels (u-timer) ? pwm timer: 4 channels ? watchdog timer: 1 channel bit search module first bit transition 1 or 0 from msb can be detected in 1 cycle interrupt controller ? external interrupt input: non-maskable interrupt (nmi ), normal interrupt 8 (int0 to int7) ? internal interrupt incident:uart, dma controller (dmac), a/d converter, u-timer and delayed interrupt module ? priority levels of interrupts are programmable except for non-maskable interrupt (in 16 levels) others ? reset cause: power-on reset/hardware standby/watchdog timer/software reset/external reset ? low-power consumption mode: sleep mode/stop mode ? clock control gear function:operating clocks for cpu and peripherals are independently selective gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16) however, operating frequency for peripherals is less than 25 mhz. ? packages: lqfp-120 ? cmos technology (0.35 m m): mb91v108 (0.25 m m) development model MB91107 (0.25 m m) production model mb91108 (0.25 m m) production model ? power supply voltage: 3.3 v 0.3 v (internal regulator) MB91107/108 4 n pin assignment (top view) (fpt-120p-m21) 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 pb5/cs1l pb6/cs1h pb7/dw1 c cs0 pa1/cs1 pa2/cs2 pa3/cs3 pa4/cs4 pa5/cs5 pa6/clk nmi hst rst v ss md0 md1 md2 p80/rdy p81/bgrnt p82/brq rd wr0 p85/wr1 p20/d16 p21/d17 p22/d18 p23/d19 p24/d20 p25/d21 pg5/int5 pg4/int4 pg3/int3 pg2/int2 pg1/int1 pg0/int0 v cc ph7/ocpa3 ph6/ocpa2 ph5/ocpa1 ph4/ocpa0 ph3/trg3/cs7 ph2/trg2/cs6 ph1/trg1 ph0/trg0 an3 an2 an1 an0 av ss /avrl avrh av cc a24/p70 a23/p67 a22/p66 a21/p65 a20/p64 a19/p63 a18/p62 a17/p61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 ras1/pb4 dw0/pb3 cs0h/pb2 cs0l/pb1 ras0/pb0 v cc x0 x1 v ss pi1/eop2/atg pi0/dack2 pe7/dreq2 pe6/eop1 pe5/dack1 pe4/dreq1 pe3/eop0 pe2/dack0 pe1/dreq0 pe0/sc2 pf7/so2 pf6/si2 pf5/sc1 pf4/so1 pf3/si1 pf2/sc0 pf1/so0 v ss pf0/si0 pg7/int7 pg6/int6 p26/d22 p27/d23 d24 d25 d26 d27 d28 d29 d30 d31 v ss a00 a01 a02 a03 a04 a05 a06 a07 v cc a08 a09 a10 a11 a12 a13 a14 a15 v ss p60/a16 MB91107/108 5 n pin description (continued) pin no. pin name circuit type function 85 86 87 88 89 90 91 92 d16/p20 d17/p21 d18/p22 d19/p23 d20/p24 d21/p25 d22/p26 d23/p27 c bit 16 to bit 23 of external data bus. can be configured as ports (p20 to p27) when external data bus width is set to 8-bit. 93 94 95 96 97 98 99 100 d24 d25 d26 d27 d28 d29 d30 d31 c bit 24 to bit 31 of external data bus. 102 103 104 105 106 107 108 109 111 112 113 114 115 116 117 118 a00 a01 a02 a03 a04 a05 a06 a07 a08 a09 a10 a11 a12 a13 a14 a15 f bit 00 to bit 15 of external address bus. 120 1 2 3 4 5 6 7 a16/p60 a17/p61 a18/p62 a19/p63 a20/p64 a21/p65 a22/p66 a23/p67 f bit 16 to bit 23 of external address bus. can be configured as ports(p60 to p67) when not used as address bus. 8a24/p70f bit 24 of external address bus. can be configured as a port(p70) when not used as address bus. 79 rdy/p80 c external ready input. inputs 0 when bus cycle is being executed and not completed. can be configured as a port when this pin is not used. MB91107/108 6 (continued) pin no. pin name circuit type function 80 bgrnt /p81 f external bus release acknowledge output. outputs l level when external bus is released. can be configured as a port when this pin is not used. 81 brq/p82 p external bus release request input. inputs 1 when release of external bus is required. can be configured as a port when this pin is not used. 82 rd m read strobe output pin for external bus. 83 wr0 m write strobe output pin for external bus. relation between control signals and effective byte locations is as follows: note: wr1 is hi-z during resetting. attach an external pull-up resister when using at 16-bit bus width. 84 wr1 /p85 f 65 cs0 m chip select 0 output (l active). 66 67 68 69 70 cs1 /pa1 cs2 /pa2 cs3 /pa3 cs4 /pa4 cs5 /pa5 f chip select 1 output (l active). chip select 2 output (l active). chip select 3 output (l active). chip select 4 output (l active). chip select 5 output (l active). can be configured as ports when pa1 to pa5 are not used. 71 clk/pa6 f system clock output. outputs clock signal of external bus operating frequency. can be configured as a port when pa6 is not used. 56 57 58 59 60 61 62 63 ras0/pb0 cs0l/pb1 cs0h/pb2 dw0 /pb3 ras1/pb4 cs1l/pb5 cs1h/pb6 dw1 /pb7 f ras output for dram bank 0. casl output for dram bank 0. cash output for dram bank 0. we output for dram bank 0 (l active). ras output for dram bank 1. casl output for dram bank 1. cash output for dram bank 1. we output for dram bank 1 (l active) can be configured as a port when pb0 to pb7 are not used. 76 77 78 md0 md1 md2 g mode pins 0 to 2. mcu basic operation mode is set by these pins. directly connect these pins with v cc or v ss for use. 53 54 x1 x0 a clock (oscillator) output. clock (oscillator) input. 74 rst b external reset input. 73 hst h hardware standby input (l active). 16-bit bus width 8-bit bus width d31 to d24 wr0 wr0 d23 to d16 wr1 (i/o port enabled) refer to the dram interface for details. ? ? ? ? y ? MB91107/108 7 (continued) pin no. pin name circuit type function 72 nmi h nmi (non-maskable interrupt pin) input (l active). 42 sc2/pe0 f (sc2) clock i/o pin for uart2. clock output is available when clock output of uart2 is enabled. (pe0) general purpose i/o port. this function is available when uart2 clock output is disabled. 43 dreq0/pe1 f (dreq0) external transfer request input pins for dma. this pin is used for input when external trigger is selected to cause dmac operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. (pe1) general purpose i/o port. 44 dack0/pe2 f (dack0) external transfer request acknowledge output pin for dmac (ch. 0). this function is available when transfer request output for dmac is enabled. (pe2) general purpose i/o port. this function is available when transfer request acknowledge output for dmac or dack0 output is disabled. 45 eop0/pe3 f (eop0) can be configured as dmac eop output (ch.0) when dmac eop output is enable. (pe3) general purpose i/o port. 46 dreq1/pe4 f (dreq1) external transfer request input pins for dma. this pin is used for input when external trigger is selected to cause dmac operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. (pe4) general purpose i/o port. 47 dack1/pe5 f (dack1) external transfer request acknowledge output pin for dmac (ch. 1). this function is available when transfer request output for dmac is enabled. (pe5) general purpose i/o port. this function is available when transfer request acknowledge output for dmac or dack1 output is disabled. 48 eop1/pe6 f (eop1) can be configured as dmac eop output (ch.1) when dmac eop output is enable. (pe6) general purpose i/o port. 49 dreq2/pe7 f (dreq2) external transfer request input pins for dma. this pin is used for input when external trigger is selected to cause dmac operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. (pe7) general purpose i/o port. MB91107/108 8 (continued) pin no. pin name circuit type function 33 si0/pf0 f (si0) uart0 data input pin. this pin is used for input during uart0 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. (pf0) general purpose i/o port. 35 so0/pf1 f (so0) uart0 data output pin. this function is available when uart0 data output is enabled. (pf1) general purpose i/o port. this function is available when uart0 data output is disabled. 36 sc0/pf2 f (sc0) uart0 clock i/o pin. clock output is available when uart0 clock output is enabled. (pf2) general purpose i/o port. this function is available when uart0 clock output is disabled. 37 si1/pf3 f (si1) uart1 data input pin. this pin is used for input during uart1 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. (pf3) general purpose i/o port. 38 so1/pf4 f (so1) uart1 data output pin. this function is available when uart1 data output is enabled. (pf4) general purpose i/o port. this function is available when uart1 data output is disabled. 39 sc1/pf5 f (sc1) clock i/o pin for uart1. clock output is available when clock output of uart1 is enabled. (pf5) general purpose i/o port. this function is available when uart1 clock output is disabled. 40 si2/pf6 f (si2) uart2 data input pin. this pin is used for input during uart2 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. (pf6) general purpose i/o port. 41 so2/pf7 f (so2) uart2 data output pin. this function is available when uart2 data output is enabled. (pf7) general purpose i/o port. this function is available when uart2 data output is disabled. MB91107/108 9 (continued) pin no. pin name circuit type function 25 26 27 28 29 30 31 32 int0/pg0 int1/pg1 int2/pg2 int3/pg3 int4/pg4 int5/pg5 int6/pg6 int7/pg7 i (int0 to int7) external interrupt request input pin. this pin is used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. (pg0 and pg7) general purpose i/o port. 16 17 trg0/ph0 trg1/ph1 f (trg0 and trg1) pwm timer external trigger input pin. this function is available when ph0 and ph1 data outputs are disabled. (ph0 and ph1) general purpose i/o port. 18 19 trg2/ph2/ cs6 trg3/ph3/ cs7 f (trg2 and trg3) pwm timer external trigger input pin. this function is available when ph2 and ph3 data outputs are disabled. (ph2 and ph3) can be configured as a i/o port when trg2, trg3, cs6 and cs7 are not used. chip select 6 output (l active). chip select 7 output (l active). 20 21 22 23 ocpa0/ph4 ocpa1/ph5 ocpa2/ph6 ocpa3/ph7 f (ocpa0 to ocpa3) pwm timer output pin. this function is available when pwm timer output is enabled. (ph4 to ph7) general purpose i/o port. 50 dack2/pi0 f (dack2) external transfer request acknowledge output pin for dmac (ch. 2). this function is available when transfer request output for dmac is enabled. (pi0) general purpose i/o port. this function is available when transfer request acknowledge output for dmac or dack2 output is disabled. 51 eop2/pi1/ atg f (eop2) eop output pin for dmac (ch.1). this function is available when eop output for dmac is enabled. (pi1) general purpose i/o port. this function is available when transfer complete acknowledge output for dmac output is disabled. (atg )external trigger input pin for a/d converter. this pin is used for input when external trigger is selected to cause a/d converter operation, and it is necessary to disable output for other func- tions from this pin unless such output is made intentionally. 12 to 15 an0 to an3 n (an0 to an3) analog input pins of a/d converter. this function is available when aic register is set to specify analog input mode. 9av cc ? power supply pin (v cc ) for a/d converter. 10 avrh ? reference voltage input (high) for a/d converter. make sure to turn on and off this pin with potential of avrh or more ap- plied to v cc . MB91107/108 10 (continued) note : in most of the above pins, i/o port and resource i/o are multiplexed e.g. xxx/pxxx. in case of conflict between output of i/o port and resource i/o, priority is always given to the output of resource i/o. n dram control register pin no. pin name circuit type function 11 av ss / avrl ? power supply pin (v ss ) for a/d converter and reference voltage input pin (low). 24, 55, 110 v cc ? power supply pin (v cc ) for digital circuit. always three pins must be connected to the power supply 64 c ? bypass capacitor pin for internal capacitor. refer to the handling devices. 34, 52, 75, 101, 119 v ss ? earth level (v ss ) for digital circuit. pin name data bus 16-bit mode data bus 8-bit mode remarks 2cas/1wr mode 1cas/2wr mode ras0 area 4 ras area 4 ras area 4 ras correspondence of l h to lower ad- dress 1 bit (a0) in data bus 16-bit mode. l: 0 h: 1 casl : cas which a0 corresponds to 0 area cash : cas which a0 corresponds to 1 area wel : we which a0 corresponds to 0 area weh : we which a0 corresponds to 1 ras1 area 5 ras area 5 ras area 5 ras cs0l area 4 casl area 4 cas area 4 cas cs0h area 4 cash area 4 wel area 4 cas cs1l area 5 casl area 5 cas area 5 cas cs1h area 5 cash area 5 wel area 5 cas dw0 area 4 we area 4 wel area 4 we dw1 area 5 we area 5 wel area 5 we MB91107/108 11 n i/o circuit type (continued) type circuit remarks a ? oscillation feedback resistance: 1 m w approx. b ? cmos level hysteresis input without standby control ? with pull-up resistance c ? cmos level i/o with standby control n ? analog input x1 standby control x0 clock input v ss v cc diffused resistor p-channel type tr. n-channel type tr. digital input standby control digital output digital input digital output analog input MB91107/108 12 (continued) type circuit remarks f ? cmos level output ? cmos level hysteresis input with standby control g ? cmos level input without standby control h ? cmos level hysteresis input without standby control i ? cmos level output ? cmos level hysteresis input without standby control standby control digital output digital output digital input digital input digital input digital input digital output digital output MB91107/108 13 (continued) type circuit remarks m ? cmos level output p ? cmos level output ? cmos level input with standby control ? with pull-down resistance digital output digital output standby control pull-down resistor control digital output digital output digital input MB91107/108 14 n handling devices 1. preventing latchup in cmos ics, applying voltage higher than v cc or lower than v ss to input/output pin or applying voltage over rating across v cc and v ss may cause latchup. this phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the device. make sure to prevent the voltage from exceeding the maximum rating. 2. treatment of pins treatment of unused pins unused pins left open may cause malfunctions. make sure to connect them to pull-up or pull-down resistors. handling the output pins connecting an output pin to the power supply, to another output pin, or to a large-capacitance load may cause a large current to flow. since letting it flow for an extended period of time degrades the device, be careful in using the device not to exceed the maximum rating. power supply pins when there are several v cc and v ss pins, each of them is equipotentially connected to its counterpart inside of the device, minimizing the risk of malfunctions such as latch up. to further reduce the risk of malfunctions, to prevent emi radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and to observe the total output current standard, connect all v cc and v ss pins to the power supply or gnd. it is preferred to connect v cc and v ss of MB91107 to power supply with minimal impedance possible. it is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1 m f between v cc and v ss at a position as close as possible to MB91107. mode setting p ins (md0 to md2) connect mode setting pins (md0 to md2) directly to v cc or v ss . arrange each mode setting pin and v cc or v ss patterns on the printed circuit board as close as possible and make the impedance between them minimal to prevent mistaken entrance to the test mode caused by noises. crystal oscillator circuit noises around x0 and x1 pins may cause malfunctions of mb91101. in designing the pc board, layout x0, x1 and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible. it is strongly recommended to design pc board so that x1 and x0 pins are surrounded by grounding area for stable operation. 3. notes on use external reset input the rst pin requires "l" level input for at least five machine cycles before the the internal circuitry can be completely reset. external clock to use an external clock, in principle, supply the x0 and x1 pins with a clock signal opposite in phase to the x0. to use the stop mode (oscillation stop mode) along with the external clock, in which the x1 pin stops with "h" output, you should insert an external resistor of about 1 kilohm to prevent a collision between outputs. given the next page is an example of using an external clock. MB91107/108 15 4. notes on internal dc-dc regulator ? since this product contains a regulator, be sure to supply current at 3.3 v to the vcc pin and insert a bypass capacitor of about 0.1 m f to the c pin for the regulator. ? the a/d converter requires a 3.3-v power supply separately. ?notes on using the stop mode the regulator built in this product stops in the stop mode. if the regulator stops due to a malfunction caused by noise or a fault in the power supply during normal operation, the internal 2.5-v power supply may go below the lower limit of the guaranteed operating voltage range. when using the stop mode with the internal regulator, therefore, be sure to supply an auxiliary external power to prevent the 3.3-v power supply from coming down. even in that case, the internal regulator can be restarted by input of a reset signal (to restart the regulator, keep the reset pin at the l level for at least the oscillation settling time). ?using an external clock (for normal use) x0 x1 note: to use the stop mode (oscillation stop mode), insert a resistor to the x1 pin. mb91108 MB91107 3.3 v gnd v cc av cc avrh av ss v ss c ?connecting to power supply MB91107/108 16 5. turning on the power supply rst pin when turning on the power supply, never fail to start from setting the rst pin to l level. and after the power supply voltage goes to v cc level, at least after ensuring the time for 5 machine cycles, then set to h level. pin condition at turning on the power supply the pin condition at turning on the power supply is unstable. the circuit starts being initialized after turning on the power supply and then starting oscillation and then the operation of the internal regulator becomes stable. so it takes about 42 ms for the pin to be initialized from the oscillation starting at the source oscillation 12.5 mhz. take care that the pin condition may be output condition at initial unstable condition. (with the MB91107, however, initalization can be achieved in less than about 42 ms after turning on the internal power supply by maintaining the rst pin at "l" level.) source oscillation input at turning on the power supply at turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing waiting. hardware stand-by at turning on the power supply when turning on the power supply with the hst pin being set to l level, the hardware doesnt stand by. however the hst pin becomes available after the reset cancellation, the hst pin must once be back to h level. power on reset make sure to make power on reset at turning on the power supply or returning on the power supply when the power supply voltage is below the warranty range for normal operation. ?using stop mode with 3.3 v power supply 3.3 v v cc v ss c 2.4 k w 7.6 k w 0.1 m f MB91107/108 17 n block diagram fr cpu i-bus (16 bit) d-bus (32 bit) instruction cache 1 kb harvard princeton bus converter bit search module dmac (8 ch) dreq0 dack0 eop0 dreq1 dack1 eop1 dreq2 dack2 eop2 32 bit 16 bit bus converter x0 x1 rst hst clock control unit (watch dog timer) int0 ~ int7 nmi interrupt control unit an0 ~ an3 av cc avrh av ss avrl atg 10 bit a/d converter (4 ch) reload timer (3 ch) port r-bus (16 bit) uart (3 ch) with baud rate timer pwm timer (4 ch) si0 si1 si2 so0 so1 so2 sc0 sc1 sc2 ocpa0 ~ ocpa3 trg0 ~ trg3 (32 bit) c-bus port 0 ~ port b dram controller ram 128 kb (MB91107) ram 160 kb (mb91108) bus controller ras0 cs0l cs0h dw0 ras1 cs1l cs1h dw1 d31 ~ d16 a24 ~ a00 rd wr0 ~ wr1 rdy clk cs0 ~ cs7 brq bgrnt note: pins are display for functions (actually some pins are multiplexer). when using realos, time control should be done by using external interrupt or inner timer. MB91107/108 18 n cpu core 1. memory space the fr family has a logical address space of 4 gbytes (2 32 bytes) and the cpu linearly accesses the memory space. 0000 0000 h 0000 0400 h 0000 0800 h 0001 0000 h 000c 0000 h 000e 0000 h 0010 0000 h ffff ffff h i/o i/o i/o i/o 000e 8000 h access inhibited external rom/external bus mode access inhibited direct addressing area* 1 see n i/o map *1: the following areas on the memory space are assigned to direct addressing area for i/o. in these areas, an address can be specified in a direct operand of a code. direct areas consists of the following areas dependent on accessible data sizes. *2: access inhibited of MB91107 note : only the above mode exist in this product. ? byte data access 0-0ff h ? half word data access 0-1ff h ? word data access 0-3ff h external area external area internal ram external area internal ram external area external area ? internal 32kb-ram * 2 (mb91108 only) ? internal 128 kb-ram internal rom/external bus mode access inhibited MB91107/108 19 2. registers the fr family has two types of registers; dedicated registers embedded on the cpu and general-purpose registers on memory. dedicated registers program status (ps) the ps register is for holding program status and consists of a condition code register (ccr), a system condition code register (scr) and a interrupt level mask register (ilm). program counter (pc) : 32-bit length, indicates the location of the instruction to be executed. program status (ps) : 32-bit length, register for storing register pointer or condition codes. table base register (tbr) : holds top address of vector table used in eit (exceptional/interrupt/ trap processing. return pointer (rp) : holds address to resume operation after returning from a subroutine. system stack pointer (ssp) : indicates system stack space. user's stack pointer (usp) : indicates users stack space. multiplication/division result register (mdh/mdl) : 32-bit length, register for multiplication/division. 32 bit 32 bit initial value program counter pc xxxx xxxx indeterminate program status ps ? ilm ? scr ccr table base register tbr 0 0 0f fc 0 0 return pointer rp xxxx xxxx indeterminate system stack pointer ssp 0 0 0 0 0 0 0 0 users stack pointer usp xxxx xxxx indeterminate multiplication/division re- sult register mdh xxxx xxxx indeterminate mdl xxxx xxxx indeterminate 312019181716 109876543210 ps ? ilm4 to ilm0 ? d1 d0 t ?? sinzvc ilm scr ccr MB91107/108 20 condition code register (ccr) system condition code register (scr) interrupt level mask register (ilm) s-flag : specifies a stack pointer used as r15. i-flag : controls user interrupt request enable/disable. n-flag : indicates sign bit when division result is assumed to be in the 2s complement format. z-flag : indicates whether or not the result of division was 0. v-flag : assumes the operand used in calculation in the 2s complement format and indicates whether or not overflow has occurred. c-flag : indicates if a carry or borrow from the msb has occurred. t-flag : specifies whether or not to enable step trace trap. ilm4 to ilm0 : register for holding interrupt level mask value. the value held by this register is used as a level mask. when an interrupt request issued to the cpu is higher than the level held by ilm, the interrupt request is accepted. ilm4 ilm3 ilm2 ilm1 ilm0 interrupt level high-low 00000 0high 01111 15 11111 31low MB91107/108 21 n general-purpose registers r0 to r15 are general-purpose registers embedded on the cpu. these registers functions as an accumulator and a memory access pointer. of the above 16 registers, following registers have special functions. to support the special functions, part of the instruction set has been sophisticated to have enhanced functions. r13: virtual accumulator (ac) r14: frame pointer (fp) r15: stack pointer (sp) upon reset, values in r0 to r14 are not fixed. value in r15 is initialized to be 0000 0000 h (ssp value). 32 bit initial value r0 xxxx xxxx h r1 : : :: : : r12 : r13 ac : r14 fp xxxx xxxx h r15 sp 0000 0000 h MB91107/108 22 n setting mode 1. pin mode setting pins and modes 2. registers mode data bus mode setting bits and functions note : MB91107 places 128-kb internal ram in the internal rom area. to use the 128-kb internal ram, be sure to set 01. mode setting pins mode name reset vector access area external data bus width bus mode md2 md1 md0 000 external vector mode 0 external 8 bits external rom/external bus mode 001 external vector mode 1 external 16 bits 0 1 0 inhibited 0 1 1 internal vector mode internal (mode register) inhibited 1 inhibited m1 m0 functions note 0 0 single-chip mode 0 1 internal rom/external bus mode inhibited 1 0 external rom/external bus mode 1 1 inhibited modr initial value access address : 0000 07ffh m1 m0 * ***** xxxx xxxx b w ? y ? t bus mode setting bit always write 0 except for m1 and m0. MB91107/108 23 n i/o map the remainder of this section contains a list of the registers for peripheral resources in memory space. note : do not execute an rmw-type instruction for any register containing a write-only bit. (continued) address register name register name access resource name initial value 000001 h pdr2 port 2 data registe r/w port data register xxxxxxxx b 000004 h pdr7 port 7 data registe r/w - - - - - - - x b 000005 h pdr6 port 6 data registe r/w xxxxxxxx b 000008 h pdrb port b data registe r/w xxxxxxxx b 000009 h pdra port a data registe r/w - xxxxxx - b 00000b h pdr8 port 8 data registe r/w - - x - - xxx b 000012 h pdre port e data registe r/w xxxxxxxx b 000013 h pdrf port f data registe r/w xxxxxxxx b 000014 h pdrg port g data registe r/w xxxxxxxx b 000015 h pdrh port h data registe r/w xxxxxxx0 b 000016 h pdri port i data registe r/w - - - - - - xx b 00001c h ssr0 serial status register 0 r/w uart0 0 0 0 0 1 - 0 0 b 00001d h sidr0/ sodr0 serial input data register 0/ serial output data register r/w xxxxxxxx b 00001e h scr0 serial control register 0 r/w 0 0 0 0 0 1 0 0 b 00001f h smr0 serial mode register 0 r/w 0 0 - - 0 - 0 0 b 000020 h ssr1 serial status register 1 r/w uart1 0 0 0 0 1 - 0 0 b 000021 h sidr1/ sodr1 serial input data register 1/ serial output data register r/w xxxxxxxx b 000022 h scr1 serial control register 1 r/w 0 0 0 0 0 1 0 0 b 000023 h smr1 serial mode register 1 r/w 0 0 - - 0 - 0 0 b 000024 h ssr2 serial status register 2 r/w uart2 0 0 0 0 1 - 0 0 b 000025 h sidr2/ sodr2 serial input data register 2/ serial output data register r/w xxxxxxxx b 000026 h scr2 serial control register 2 r/w 0 0 0 0 0 1 0 0 b 000027 h smr2 serial mode register 2 r/w 0 0 - - 0 - 0 0 b 000028 h tmrlr0 16-bit reload register 0 w reload timer 0 xxxxxxxx b 000029 h xxxxxxxx b 00002a h tmr0 16-bit timer register 0 r xxxxxxxx b 00002b h xxxxxxxx b 00002e h tmcsr0 16-bit reload timer control status register 0 r/w - - - - 0 0 0 0 b 00002f h 0 0 0 0 0 0 0 0 b MB91107/108 24 note : do not execute an rmw-type instruction for any register containing a write-only bit. (continued) address register name register name access resource name initial value 000030 h tmrlr1 16-bit reload register 1 w reload timer 1 xxxxxxxx b 000031 h xxxxxxxx b 000032 h tmr1 16-bit timer register 1 r xxxxxxxx b 000033 h xxxxxxxx b 000036 h tmcsr1 16-bit reload timer control status register 1 r/w - - - - 0 0 0 0 b 000037 h 0 0 0 0 0 0 0 0 b 000038 h adcr a/d converter data register r a/d converter (successive approximation type) - - - - - - xx b 000039 h xxxxxxxx b 00003a h adcs a/d converte control status register r/w 0 0 0 0 0 0 0 0 b 00003b h 0 0 0 0 0 0 0 0 b 00003c h tmrlr2 16-bit reload register 2 w reload timer 2 xxxxxxxx b 00003d h xxxxxxxx b 00003e h tmr2 16-bit timer register 2 r xxxxxxxx b 00003f h xxxxxxxx b 000042 h tmcsr2 16-bit reload timer control status register 2 r/w - - - - 0 0 0 0 b 000043 h 0 0 0 0 0 0 0 0 b 000050 h asr6 area select register 6 w external bus interface 1 1 1 1 1 1 1 1 b 000051 h 1 1 1 1 1 1 1 1 b 000052 h amr6 area mask register 6 w 0 0 0 0 0 0 0 0 b 000053 h 0 0 0 0 0 0 0 0 b 000054 h asr7 area select register 7 w 1 1 1 1 1 1 1 1 b 000055 h 1 1 1 1 1 1 1 1 b 000056 h amr7 area mask register 7 w 0 0 0 0 0 0 0 0 b 000057 h 0 0 0 0 0 0 0 0 b 000059 h cs67 output enable r/w - - - - 0 0 1 1 b 000078 h utim0/ utimr0 u-timer register ch.0 u-timer reload register ch.0 r/w u-timer 0 0 0 0 0 0 0 0 0 b 000079 h 0 0 0 0 0 0 0 0 b 00007b h utimc0 u-timer control register ch.0 r/w 0 - - 0 0 0 0 1 b MB91107/108 25 note : do not execute an rmw-type instruction for any register containing a write-only bit. (continued) address register name register name access resource name initial value 00007c h utim1/ utimr1 u-timer register ch.1 u-timer reload register ch.1 r/w u-timer 1 0 0 0 0 0 0 0 0 b 00007d h 0 0 0 0 0 0 0 0 b 00007f h utimc1 u-timer control register ch.1 r/w 0 - - 0 0 0 0 1 b 000080 h utim2/ utimr2 u-timer register ch.2 u-timer reload register ch.2 r/w u-timer 2 0 0 0 0 0 0 0 0 b 000081 h 0 0 0 0 0 0 0 0 b 000083 h utimc2 u-timer control register ch.2 r/w 0 - - 0 0 0 0 1 b 000094 h eirr external interrup request register r/w external interrupt/nmi 0 0 0 0 0 0 0 0 b 000095 h enir interrupt enabble register r/w 0 0 0 0 0 0 0 0 b 000098 h elvr external interrup request level setup register r/w 0 0 0 0 0 0 0 0 b 000099 h 0 0 0 0 0 0 0 0 b 0000d2 h ddre port e data direction register w port e-i data direction register 0 0 0 0 0 0 0 0 b 0000d3 h ddrf port f data direction register w 0 0 0 0 0 0 0 0 b 0000d4 h ddrg port g data direction register w 0 0 0 0 0 0 0 0 b 0000d5 h ddrh port h data direction register w 0 0 0 0 0 0 0 1 b 0000d6 h ddri port i data direction register w - - - - - - 0 0 b 0000dc h gcn1 general control register 1 r/w pwm 0 0 1 1 0 0 1 0 b 0000dd h 0 0 0 1 0 0 0 0 b 0000df h gcn2 general control register 2 r/w 0 0 0 0 0 0 0 0 b 0000e0 h ptmr0 pwm timer register 0 r 1 1 1 1 1 1 1 1 b 0000e1 h 1 1 1 1 1 1 1 1 b 0000e2 h pcsr0 pwm cycle setting register 0 w xxxxxxxx b 0000e3 h xxxxxxxx b 0000e4 h pdut0 pwm duty setting register 0 w xxxxxxxx b 0000e5 h xxxxxxxx b 0000e6 h pcnh0 control status register h 0 r/w 0 0 0 0 0 0 0 - b 0000e7 h pcnl0 control status register l 0 r/w 0 0 0 0 0 0 0 0 b 0000e8 h ptmr1 pwm timer register 1 r 1 1 1 1 1 1 1 1 b 0000e9 h 1 1 1 1 1 1 1 1 b 0000ea h pcsr pwm cycle setting register 1 w xxxxxxxx b 0000eb h xxxxxxxx b 0000ec h pdut pwm duty setting register 1 w xxxxxxxx b 0000ed h xxxxxxxx b 0000ee h pcnh control status register h 1 r/w 0 0 0 0 0 0 0 - b 0000ef h pcnl control status register l 1 r/w 0 0 0 0 0 0 0 0 b MB91107/108 26 note : do not execute an rmw-type instruction for any register containing a write-only bit. (continued) address register name register name access resource name initial value 0000f0 h ptmr2 pwm timer register 2 r pwm 1 1 1 1 1 1 1 1 b 0000f1 h 1 1 1 1 1 1 1 1 b 0000f2 h pcsr2 pwm cycle setting register 2 w xxxxxxxx b 0000f3 h xxxxxxxx b 0000f4 h pdut2 pwm duty setting register 2 w xxxxxxxx b 0000f5 h xxxxxxxx b 0000f6 h pcnh2 control status register h 2 r/w 0 0 0 0 0 0 0 - b 0000f7 h pcnl2 control status register l 2 r/w 0 0 0 0 0 0 0 0 b 0000f8 h ptmr3 pwm timer register 3 r 1 1 1 1 1 1 1 1 b 0000f9 h 1 1 1 1 1 1 1 1 b 0000fa h pcsr3 pwm cycle setting register 3 w xxxxxxxx b 0000fb h xxxxxxxx b 0000fc h pdut3 pwm duty setting register 3 w xxxxxxxx b 0000fd h xxxxxxxx b 0000fe h pcnh3 control status register h 3 r/w 0 0 0 0 0 0 0 - b 0000ff h pcnl3 control status register l 3 r/w 0 0 0 0 0 0 0 0 b 000200 h dpdp dmac parameter descriptor point r/w dmac xxxxxxxx b 000201 h xxxxxxxx b 000202 h xxxxxxxx b 000203 h x 0 0 0 0 0 0 0 b 000204 h dacsr dmac control status register r/w 0 0 0 0 0 0 0 0 b 000205 h 0 0 0 0 0 0 0 0 b 000206 h 0 0 0 0 0 0 0 0 b 000207 h 0 0 0 0 0 0 0 0 b 000208 h datcr dmac pin control register r/w xxxxxxxx b 000209 h xx 0 0 0 0 0 0 b 00020a h xx 0 0 0 0 0 0 b 00020b h xx 0 0 0 0 0 0 b 0003e4 h ichcr instruction cache r/w instruction cache - - - - - - - - b 0003e5 h - - - - - - - - b 0003e6 h - - - - - - - - b 0003e7 h - - 0 0 0 0 0 0 b MB91107/108 27 note : do not execute an rmw-type instruction for any register containing a write-only bit. (continued) address register name register name access resource name initial value 0003f0 h bsd0 bit search module zero-detection data register w bit search module xxxxxxxx b 0003f1 h xxxxxxxx b 0003f2 h xxxxxxxx b 0003f3 h xxxxxxxx b 0003f4 h bsd1 bit search module single-detection data register r/w xxxxxxxx b 0003f5 h xxxxxxxx b 0003f6 h xxxxxxxx b 0003f7 h xxxxxxxx b 0003f8 h bsdc bit search module transition-detection data register w xxxxxxxx b 0003f9 h xxxxxxxx b 0003fa h xxxxxxxx b 0003fb h xxxxxxxx b 0003fc h bsrr bit search module result register r xxxxxxxx b 0003fd h xxxxxxxx b 0003fe h xxxxxxxx b 0003ff h xxxxxxxx b 000400 h icr00 interrupt control register 0 r/w interrupt controller - - - 1 1 1 1 1 b 000401 h icr01 interrupt control register 1 - - - 1 1 1 1 1 b 000402 h icr02 interrupt control register 2 - - - 1 1 1 1 1 b 000403 h icr03 interrupt control register 3 - - - 1 1 1 1 1 b 000404 h icr04 interrupt control register 4 - - - 1 1 1 1 1 b 000405 h icr05 interrupt control register 5 - - - 1 1 1 1 1 b 000406 h icr06 interrupt control register 6 - - - 1 1 1 1 1 b 000407 h icr07 interrupt control register 7 - - - 1 1 1 1 1 b 000408 h icr08 interrupt control register 8 - - - 1 1 1 1 1 b 000409 h icr09 interrupt control register 9 - - - 1 1 1 1 1 b 00040a h icr10 interrupt control register 10 - - - 1 1 1 1 1 b 00040b h icr11 interrupt control register 11 - - - 1 1 1 1 1 b 00040c h icr12 interrupt control register 12 - - - 1 1 1 1 1 b 00040d h icr13 interrupt control register 13 - - - 1 1 1 1 1 b 00040e h icr14 interrupt control register 14 - - - 1 1 1 1 1 b 00040f h icr15 interrupt control register 15 - - - 1 1 1 1 1 b 000410 h icr16 interrupt control register 16 - - - 1 1 1 1 1 b MB91107/108 28 note : do not execute an rmw-type instruction for any register containing a write-only bit. (continued) address register name register name access resource name initial value 000411 h icr17 interrupt control register17 r/w interrupt controller - - - 1 1 1 1 1 b 000412 h icr18 interrupt control register 18 - - - 1 1 1 1 1 b 000413 h icr19 interrupt control register 19 - - - 1 1 1 1 1 b 000414 h icr20 interrupt control register 20 - - - 1 1 1 1 1 b 000415 h icr21 interrupt control register 21 - - - 1 1 1 1 1 b 000416 h icr22 interrupt control register 22 - - - 1 1 1 1 1 b 000417 h icr23 interrupt control register 23 - - - 1 1 1 1 1 b 000418 h icr24 interrupt control register 24 - - - 1 1 1 1 1 b 000419 h icr25 interrupt control register 25 - - - 1 1 1 1 1 b 00041a h icr26 interrupt control register 26 - - - 1 1 1 1 1 b 00041b h icr27 interrupt control register 27 - - - 1 1 1 1 1 b 00041c h icr28 interrupt control register 28 - - - 1 1 1 1 1 b 00041d h icr29 interrupt control register 29 - - - 1 1 1 1 1 b 00041e h icr30 interrupt control register 30 - - - 1 1 1 1 1 b 00041f h icr31 interrupt control register 31 - - - 1 1 1 1 1 b 000420 h icr32 interrupt control register 32 - - - 1 1 1 1 1 b 000421 h icr33 interrupt control register 33 - - - 1 1 1 1 1 b 000422 h icr34 interrupt control register 34 - - - 1 1 1 1 1 b 000423 h icr35 interrupt control register 35 - - - 1 1 1 1 1 b 000424 h icr36 interrupt control register 36 - - - 1 1 1 1 1 b 000425 h icr37 interrupt control register 37 - - - 1 1 1 1 1 b 000426 h icr38 interrupt control register 38 - - - 1 1 1 1 1 b 000427 h icr39 interrupt control register 39 - - - 1 1 1 1 1 b 000428 h icr40 interrupt control register 40 - - - 1 1 1 1 1 b 000429 h icr41 interrupt control register 41 - - - 1 1 1 1 1 b 00042a h icr42 interrupt control register 42 - - - 1 1 1 1 1 b 00042b h icr43 interrupt control register 43 - - - 1 1 1 1 1 b 00042c h icr44 interrupt control register 44 - - - 1 1 1 1 1 b 00042d h icr45 interrupt control register 45 - - - 1 1 1 1 1 b 00042e h icr46 interrupt control register 46 - - - 1 1 1 1 1 b 00042f h icr47 interrupt control register 47 - - - 1 1 1 1 1 b 000430 h dicr delayed interrupt r/w delayed interrupt controller register - - - - - - - 0 b 000431 h hrcl holding request withdrawal request level set register r/w - - - 1 1 1 1 1 b MB91107/108 29 note : do not execute an rmw-type instruction for any register containing a write-only bit. (continued) address register name register name access resource name initial value 000480 h rsrr/ wtcr reset cause register/watchdog cycle control register r/w clock controller 1 xxxx - 0 0 b 000481 h stcr stand-by controller register r/w 0 0 0 1 1 1 - - b 000482 h pdrr dma controller request prohibit resister r/w - - - - 0 0 0 0 b 000483 h ctbr timebase timer clear register w xxxxxxxx b 000484 h gcr gear controller register r/w 1 1 0 0 1 1 - 1 b 000485 h wpr watchdog reset generation postpone register w xxxxxxxx b 000488 h pctr pll controller register w pll controller 0 0 - - 0 - - - b 000601 h ddr2 port 2 data direction register w port direction register 0 0 0 0 0 0 0 0 b 000604 h ddr7 port 7 data direction register w - - - - - - - 0 b 000605 h ddr6 port 6 data direction register w 0 0 0 0 0 0 0 0 b 000608 h ddrb port b data direction register w 0 0 0 0 0 0 0 0 b 000609 h ddra port a data direction register w - 0 0 0 0 0 0 - b 00060b h ddr8 port 8 data direction register w - - 0 0 0 0 0 0 b 00060c h asr1 area selection register 1 w external bus interface 0 0 0 0 0 0 0 0 b 00060d h 0 0 0 0 0 0 0 1 b 00060e h amr1 area mask register 1 w 0 0 0 0 0 0 0 0 b 00060f h 0 0 0 0 0 0 0 0 b 000610 h asr2 area selection register 2 w 0 0 0 0 0 0 0 0 b 000611 h 0 0 0 0 0 0 1 0 b 000612 h amr2 area mask register 2 w 0 0 0 0 0 0 0 0 b 000613 h 0 0 0 0 0 0 0 0 b 000614 h asr3 area selection register 3 w 0 0 0 0 0 0 0 0 b 000615 h 0 0 0 0 0 0 11 b 000616 h amr3 area mask register 3 w 0 0 0 0 0 0 0 0 b 000617 h 0 0 0 0 0 0 0 0 b 000618 h asr4 area selection register 4 w 0 0 0 0 0 0 0 0 b 000619 h 0 0 0 0 0 1 0 0 b 00061a h amr4 area mask register 4 w 0 0 0 0 0 0 0 0 b 00061b h 0 0 0 0 0 0 0 0 b 00061c h asr5 area selection register 5 w 0 0 0 0 0 0 0 0 b 00061d h 0 0 0 0 0 1 0 1 b MB91107/108 30 (continued) note: do not execute an rmw-type instruction for any register containing a write-only bit. note : rmw-type instructions (rmw: read modify write) address register name register name access resource name initial value 00061e h amr5 area mask register 5 w external bus interface 0 0 0 0 0 0 0 0 b 00061f h 0 0 0 0 0 0 0 0 b 000620 h amd0 area mode register 0 r/w - - - 0 0 1 1 1 b 000621 h amd1 area mode register 1 r/w 0 - - 0 0 0 0 0 b 000622 h amd32 area mode register 32 r/w 0 0 0 0 0 0 0 0 b 000623 h amd4 area mode register 4 r/w 0 - - 0 0 0 0 0 b 000624 h amd5 area mode register 5 r/w 0 - - 0 0 0 0 0 b 000625 h dscr dram signal control register w 0 0 0 0 0 0 0 0 b 000626 h rfcr refresh control register r/w - - xxxxxx b 000627 h 0 0 - - - 0 0 0 b 000628 h epcr0 external pin control register 0 w - - - - 1 1 0 0 b 000629 h - 1 1 1 1 1 1 1 b 00062a h epcr1 external pin control register 1 w - - - - - - - 1 b 00062b h 1 1 1 1 1 1 1 1 b 00062c h dmcr4 dram control register 4 r/w 0 0 0 0 0 0 0 0 b 00062d h 0 0 0 0 0 0 0 - b 00062e h dmcr5 dram control register 5 r/w 0 0 0 0 0 0 0 0 b 00062f h 0 0 0 0 0 0 0 - b 0007fe h ler little endian register w little endian registor mode register - - - - - 0 0 0 b 0007ff h modr mode register w xxxxxxxx b and rj, @ri or rj, @ri eor rj, @ri andh rj, @ri orh rj, @ri eorh rj, @ri andb rj, @ri orb rj, @ri eorb rj, @ri bandl #u4, @ri borl #u4, @ri beorl #u4, @ri bandh #u4, @ri borh #u4, @ri beorh #u4, @ri MB91107/108 31 n interrupt causes, interrupt vectors and interrupt control register allocations (continued) interrupt causes interrupt number interrupt level tbr default address decimal hexadecimal register offset reset 0 00 ? 3fc h 0ffffc h reserved for system 1 01 ? 3f8 h 0ffff8 h reserved for system 2 02 ? 3f4 h 0ffff4 h reserved for system 3 03 ? 3f0 h 0ffff0 h reserved for system 4 04 ? 3ec h 0fffec h reserved for system 5 05 ? 3e8 h 0fffe8 h reserved for system 6 06 ? 3e4 h 0fffe4 h reserved for system 7 07 ? 3e0 h 0fffe0 h reserved for system 8 08 ? 3dc h 0fffdc h reserved for system 9 09 ? 3d8 h 0fffd8 h reserved for system 10 0a ? 3d4 h 0fffd4 h reserved for system 11 0b ? 3d0 h 0fffd0 h reserved for system 12 0c ? 3cc h 0fffcc h reserved for system 13 0d ? 3c8 h 0fffc8 h exception for undefined instruction 14 0e ? 3c4 h 0fffc4 h nmi request 15 0f f h fixed 3c0 h 0fffc0 h external interrupt 0 16 10 icr00 3bc h 0fffbc h external interrupt 1 17 11 icr01 3b8 h 0fffb8 h external interrupt 2 18 12 icr02 3b4 h 0fffb4 h external interrupt 3 19 13 icr03 3b0 h 0fffb0 h uart0 receive complete 20 14 icr04 3ac h 0fffac h uart1 receive complete 21 15 icr05 3a8 h 0fffa8 h uart2 receive complete 22 16 icr06 3a4 h 0fffa4 h uart0 transmit complete 23 17 icr07 3a0 h 0fffa0 h uart1 transmit complete 24 18 icr08 39c h 0fff9c h uart2 transmit complete 25 19 icr09 398 h 0fff98 h dmac0 (complete, error) 26 1a icr10 394 h 0fff94 h dmac1 (complete, error) 27 1b icr11 390 h 0fff90 h dmac2 (complete, error) 28 1c icr12 38c h 0fff8c h dmac3 (complete, error) 29 1d icr13 388 h 0fff88 h dmac4 (complete, error) 30 1e icr14 384 h 0fff84 h dmac5 (complete, error) 31 1f icr15 380 h 0fff80 h dmac6 (complete, error) 32 20 icr16 37c h 0fff7c h dmac7 (complete, error) 33 21 icr17 378 h 0fff78 h MB91107/108 32 (continued) *: when using in realos/fr, interrupt 0x40, 0x41 for system code. interrupt causes interrupt number interrupt level tbr default address decimal hexadecimal register offset a/d converter (successive approximation conversion type) 34 22 icr18 374 h 0fff74 h reload timer 0 35 23 icr19 370 h 0fff70 h reload timer 1 36 24 icr20 36c h 0fff6c h reload timer 2 37 25 icr21 368 h 0fff68 h pwm0 38 26 icr22 364 h 0fff64 h pwm1 39 27 icr23 360 h 0fff60 h pwm2 40 28 icr24 35c h 0fff5c h pwm3 41 29 icr25 358 h 0fff58 h u-timer0 42 2a icr26 354 h 0fff54 h u-timer1 43 2b icr27 350 h 0fff50 h u-timer2 44 2c icr28 34c h 0fff4c h reserved for system 45 2d icr29 348 h 0fff48 h reserved for system 46 2e icr30 344 h 0fff44 h reserved for system 47 2f icr31 340 h 0fff40 h reserved for system 48 30 icr32 33c h 0fff3c h reserved for system 49 31 icr33 338 h 0fff38 h reserved for system 50 32 icr34 334 h 0fff34 h reserved for system 51 33 icr35 330 h 0fff30 h reserved for system 52 34 icr36 32c h 0fff2c h reserved for system 53 35 icr37 328 h 0fff28 h reserved for system 54 36 icr38 324 h 0fff24 h reserved for system 55 37 icr39 320 h 0fff20 h reserved for system 56 38 icr40 31c h 0fff1c h reserved for system 57 39 icr41 318 h 0fff18 h reserved for system 58 3a icr42 314 h 0fff14 h reserved for system 59 3b icr43 310 h 0fff10 h reserved for system 60 3c icr44 30c h 0fff0c h reserved for system 61 3d icr45 308 h 0fff08 h reserved for system 62 3e icr46 304 h 0fff04 h delayed interrupt cause bit 63 3f icr47 300 h 0fff00 h reserved for system (used in realos*) 64 40 ? 2fc h 0ffefc h reserved for system (used in realos*) 65 41 ? 2f8 h 0ffef8 h used in int instructions 66 to 255 42 to ff ? 2f4 h to 000 h 0ffef4 h to 0ffc00 h MB91107/108 33 n peripheral resources 1. i/o ports there are 2 types of i/o port register structure; pdr (port data register) and ddr (data direction register) . ? for input (ddr = 0) setting; pdr reading operation: reads level of corresponding external pin. pdr writing operation: writes set value to pdr. ? for output (ddr = 1) setting; pdr reading operation: reads pdr value. pdr writing operation: outputs pdr value to corresponding external pin. (1) register configuration ?port data register (pdr) address bit 7 bit 0 initial value access 000001 h pdr2 xxxxxxxx b r/w 000005 h pdr6 xxxxxxxx b r/w 000004 h pdr7 - - - - - - - x b r/w 00000b h pdr8 - - x - - xxx b r/w 000009 h pdra - xxxxxx - b r/w 000008 h pdrb xxxxxxxx b r/w 000012 h pdre xxxxxxxx b r/w 000013 h pdrf xxxxxxxx b r/w 000014 h pdrg xxxxxxxx b r/w 000015 h pdrh xxxxxxx0 b r/w 000016 h pdri - - - - - - xx b r/w r/w : readable and writable - : unused x : indeterminate MB91107/108 34 ?data direction register (ddr) address bit 7 bit 0 initial value access 000601 h ddr2 0 0 0 0 0 0 0 0 b w 000605 h ddr6 0 0 0 0 0 0 0 0 b w 000604 h ddr7 - - - - - - - 0 b w 00060b h ddr8 - - 0 - - 0 0 0 b w 000609 h ddra - 0 0 0 0 0 0 - b w 000608 h ddrb 0 0 0 0 0 0 0 0 b w 0000d2 h ddre 0 0 0 0 0 0 0 0 b w 0000d3 h ddrf 0 0 0 0 0 0 0 0 b w 0000d4 h ddrg 0 0 0 0 0 0 0 0 b w 0000d5 h ddrh 0 0 0 0 0 0 0 1 b w 0000d6 h ddri - - - - - - 0 0 b w w : write only - : unused MB91107/108 35 (2) block diagram pdr ddr 1 0 1 0 data bus pin pdr read pdr : port data register ddr : data direction register resource input resource output enable resource output MB91107/108 36 2. dma controller (dmac) the dma controller is a module embedded in fr family devices, and performs dma (direct memory access) transfer. dma transfer performed by the dma controller transfers data without intervention of cpu, contributing to en- hanced performance of the system. ? 8 channels ? mode: single/block transfer, burst transfer and continuous transfer: 3 kinds of transfer ? transfer all through the area ? max. 65536 of transfer cycles ? interrupt function right after the transfer ? selectable for address transfer increase/decrease by the software ? external transfer request input pin, external transfer request accept output pin, external transfer complete output pin three pins for each (1) register configuration dmac (dmac internal registers) ram (dma descriptor) address bit 31 bit 0 dmac parameter descriptor point 000200 h dpdp dpdp dmac control status register 000204 h dacsr dacsr dmac pin control register 000208 h datcr datcr bit 31 bit 0 dpdp + 0 h dma ch-0 descriptor dpdp + 0c h dma ch-1 descriptor : : dpdp + 54 h dma ch-7 descriptor MB91107/108 37 (2) block diagram dreq0 ~ dreq2 dack0 ~ dack2 eop0 ~ eop2 blk dec inc / dec blk 3 3 3 3 8 5 dpdp dacsr datcr dmact sadr dadr edge/level detection circuit sequencer switcher data buffer mode data bus inner resource transfer request interrupt request MB91107/108 38 3. uart the uart is a serial i/o port for supporting asynchronous (start-stop system) communication or clk synchro- nous communication, and it has the following features. the MB91107 consists of 3 channels of uart. ? full double double buffer ? both a synchronous (start-stop system) communication and clk synchronous communication are available. ? supporting multi-processor mode ? perfect programmable baud rate any baud rate can be set by internal timer (refer to section 4. u-timer). ? any baud rate can be set by external clock. ? error checking function (parity, framing and overrun) ? transfer signal: nrz code ? enable dma transfer/start by interrupt. (1) register configuration ?serial control register address bit 15 bit 8 bit 7 bit 0 initial value access scr0 : scr1 : scr2 : 00001e h 000022 h 000026 h scr0 to scr2 (smr) 0 0 0 0 010 0 b r/w ?serial mode register address bit 15 bit 8 bit 7 bit 0 initial value access smr0 : smr1 : smr2 : 00001f h 000023 h 000027 h (scr) smr0 to smr2 0 0 - - 0 - 0 0 b r/w ?serial status register address bit 15 bit 8 bit 7 bit 0 initial value access ssr0 : ssr1 : ssr2 : 00001c h 000020 h 000024 h ssr0 to ssr2 (sidr/sodr) 0 0 0 01 - 0 0 b r/w ?serial input data register address bit 15 bit 8 bit 7 bit 0 initial value access sidr0 : sidr1 : sidr2 : 00001d h 000021 h 000025 h (ssr) (sidr/sodr) xxxxxxxx b r ?serial output data register address bit 15 bit 8 bit 7 bit 0 initial value access sidr0 : sidr1 : sidr2 : 00001d h 000021 h 000025 h (ssr) (sidr/sodr) xxxxxxxx b r r/w : readable and writable - : unused r : read only x : indeterminate w : write only MB91107/108 39 (2) block diagram si md1 md0 cs0 scke soe pen p sbl cl a/d rec rxe txe pe ore fre rdrf tdre rie tie sc r - bus sidr sodr control signal from u-timer from external clock (receive data) clock select circuit receive status judge circuit receive error generate sig- nal for dma ( to dmac) receive control circuit start bit detect circuit receive bit counter receive parity counter receive shifter receive complete receive interrupt ( to cpu) sc (clock) transmit interrupt ( to cpu) transmit start circuit transmit bit counter transmit parity counter transmit shifter transmit start so (transmit data) smr register control signals scr regis t er ssr register receive clock transmit control circuit transmit clock MB91107/108 40 4. u-timer (16-bit timer for uart baud rate generation) the u-timer is a 16-bit timer for generating uart baud rate. combination of chip operating frequency and reload value of u-timer allows flexible setting of baud rate. the u-timer operates as an interval timer by using interrupt issued on counter underflow. the MB91107 has 3 channel u-timer embedded on the chip. an interval of up to 2 16 f can be counted. (1) register configuration ? u-timer register ch 0 to ch 2 address bit 15 bit 0 initial value access utim0 : utim1 : utim2 : 000078 h 00007c h 000080 h utim0 to utim2 0 0 0 0 0 0 0 0 b 0 0 0 0 0 0 0 0 b r ? u-timer reload register ch 0 to ch 2 address bit 15 bit 0 initial value access utim0 : utim1 : utim2 : 000078 h 00007c h 000080 h utim0 to utim2 0 0 0 0 0 0 0 0 b 0 0 0 0 0 0 0 0 b w ? u-timer control register ch 0 to ch 2 address bit 15 bit 0 initial value access utim0 : utim1 : utim2 : 00007b h 00007f h 000083 h (vacancy) utimc0 to utimc2 0 - - 0 0 0 0 1 b r/w r/w : readable and writable r : read only w : write only - : unused MB91107/108 41 (2) block diagram 15 0 15 0 f f.f. clock utimr (reload register) utim (timer) load underflow control to uart (peripheral clock) MB91107/108 42 5. pwm timer the pwm timer can output high accurate pwm waves efficiently. mb91101 has inner 4-channel pwm timers, and has the following features. ? each channel consists of a 16-bit down counter, a 16-bit data resister with a buffer for cycle setting, a 16-bit compare resister with a buffer for duty setting, and a pin controller. ? the count clock of a 16-bit down counter can be selected from the following four inner clocks. ? inner clock f , f /4, f /16, f /64 ? the counter value can be initialized ffff h by the resetting or the counter borrow. ? pwm output (each channel) ? resister description cycle setting register: reload data register with a buffer duty factor setting register: compare register with a buffer transfer from the buffers uses the counter borrow method. ? pin control outline set to 1 at a duty factor match. (preferential) set to 0 at a counter borrow. the output value fixed mode is available, which makes all l (or h) output easy. the polarity can also be specified. ? interrupt requests can be generated by selected a combination of events: this timer is activated. a counter borrow is generated (cycle match). a duty factor match is generated. a counter borrow is generated (cycle match) or a duty factor match is generated. dma transfer can be invoked by the above interrupt request. ? simultaneous activation of multiple channels of the pwm timer can be set by software or by using another interval timer. restarting the pwm timer during operation can also be set. MB91107/108 43 (1) register configuration address bit 15 bit 0 initial value access 0000dc h gcn1 0 0 1 1 0 0 1 0 b 0 0 0 1 0 0 0 0 b r/w general control register 1 0000df h gcn2 0 0 0 0 0 0 0 0 b r/w general control register 2 0000e0 h ptmr 1 1 1 1 1 1 1 1 b 1 1 1 1 1 1 1 1 b r ch0 timer register 0000e2 h pcsr xxxxxxxx b xxxxxxxx b w ch0 cycle setting register 0000e4 h pdut xxxxxxxx b xxxxxxxx b w ch0 duty setting register 0000e6 h pcnh pcnl 0 0 0 0 0 0 0 - b 0 0 0 0 0 0 0 0 b r/w ch0 control status register 0000e8 h ptmr 1 1 1 1 1 1 1 1 b 1 1 1 1 1 1 1 1 b r ch1 timer register 0000ea h pcsr xxxxxxxx b xxxxxxxx b w ch1 cycle setting register 0000ec h pdut xxxxxxxx b xxxxxxxx b w ch1 duty setting register 0000ee h pcnh pcnl 0 0 0 0 0 0 0 - b 0 0 0 0 0 0 0 0 b r/w ch1 control status register 0000f0 h ptmr 1 1 1 1 1 1 1 1 b 1 1 1 1 1 1 1 1 b r ch2 timer register 0000f2 h pcsr xxxxxxxx b xxxxxxxx b w ch2 cycle setting register 0000f4 h pdut xxxxxxxx b xxxxxxxx b w ch2 duty setting register 0000f6 h pcnh pcnl 0 0 0 0 0 0 0 - b 0 0 0 0 0 0 0 0 b r/w ch2 control status register 0000f8 h ptmr 1 1 1 1 1 1 1 1 b 1 1 1 1 1 1 1 1 b r ch3 timer register 0000fa h pcsr xxxxxxxx b xxxxxxxx b (w) ch3 cycle setting register 0000fc h pdut xxxxxxxx b xxxxxxxx b w ch3 duty setting register 0000fe h pcnh pcnl 0 0 0 0 0 0 0 - b 0 0 0 0 0 0 0 0 b r/w ch3 control status register r/w : readable and writable - : unused r : read only x : indeterminate w : write only MB91107/108 44 (2) block diagram ? general construction ? for one channel 4 4 pwm0 pwm1 pwm2 pwm3 16-bit reload timer ch0 16-bit reload timer ch1 general con- trol register 2 external trg0 to trg3 general control register 1 (cause selection) trg input pwm timer ch0 trg input pwm timer ch1 trg input pwm timer ch2 trg input pwm timer ch3 1/1 ck cmp s r q irq 1/4 1/16 1/64 pcsr pdut prescaler peripheral clock 16-bit down counter load start borrow ppg mask pwm output reverse bit edge detect enable soft trigger trg input interrupt selection MB91107/108 45 6. 16-bit reload timer the 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload timer, a prescaler for generating internal count clock and control registers. internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock). the dma transfer can be started by the interruption. the MB91107 consists of 3 channels of the 16-bit reload timer. (1) register configuration ?control status register address bit 15 bit 0 initial value access tmcsr0 : tmcsr1 : tmcsr2 : 00002e h 000036 h 000042 h tmcsr0 to tmcsr2 - - - - 0 0 0 0 b 0 0 0 0 0 0 0 0 b r/w ?16-bit timer register address bit 15 bit 0 initial value access tmr0 : tmr1 : tmr2 : 00002a h 000032 h 00003e h tmr0 to tmr2 xxxxxxxx b xxxxxxxx b r ?16-bit reload register address bit 15 bit 0 initial value access tmrlr0 : tmrlr1 : tmrlr2 : 000028 h 000030 h 00003c h tmrlr0 to tmrlr2 xxxxxxxx b xxxxxxxx b w r/w : readable and writable - : unused r : read only x : indeterminate w : write only MB91107/108 46 (2) block diagram reld oute outl inte uf cnte trg out ctl. csl1 csl0 mod2 mod1 mod0 16 8 16 2 3 2 in ctl. f 2 f 2 f 2 135 3 exck gate 2 irq r | b u s uf pwm (ch 0 , ch 1) a/d (ch 2) 16-bit reload register reload 16-bit down counter retrigger clock selector prescaler clear internal clock MB91107/108 47 7. bit search module the bit search module detects transitions of data (0 to 1/1 to 0) on the data written on the input registers and returns locations of the transitions. (1) register configuration (2) block diagram address bit 31 bit 0 initial value access 0003f0 h bsd0 xxxxxxxxxxxxxxxx b xxxxxxxxxxxxxxxx b w zero-detection data register 0003f4 h bsd1 xxxxxxxxxxxxxxxx b xxxxxxxxxxxxxxxx b r/w single-detection data register 0003f8 h bsdc xxxxxxxxxxxxxxxx b xxxxxxxxxxxxxxxx b w detection data register 0003fc h bsrr xxxxxxxxxxxxxxxx b xxxxxxxxxxxxxxxx b r search result register r/w : readable and writable r : read only w : write only x : indeterminate d-bus address decoder input latch detection mode single-detection data register bit search circuit search result MB91107/108 48 8. a/d converter (successive approximation conversion type) the a/d converter is the module which converts an analog input voltage to a digital value, and it has following features. ? minimum converting time: 5.6 m s/ch. (system clock: 25 mhz) ? inner sample and hold circuit ? resolution: 10 bits ? analog input can be selected from 4 channels by program. single convert mode: 1 channel is selected and converted. scan convert mode: converting continuous channels. maximum 4 channels are programmable. continuous convert mode: converting the specified channel repeatedly. stop convert mode: after converting one channel then stop and wait till next activation synchronising at the beginning of conversion can be peformed. ? dma transfer operation is available by interruption. ? operating factor can be selected from the software, the external trigger (falling edge), and 16-bit reroad timer (rising edge). (1) register configuration ?a/d converter control register address bit 15 bit 0 initial value access 00003a h adcs 0 0 0 0 0 0 0 0 b 0 0 0 0 0 0 0 0 b r/w ?a/d converter data register address bit 15 bit 0 initial value access 000038 h adcr - - - - - -xx b xxxxxxxx b r r/w : readable and writable r : read only x : indeterminate MB91107/108 49 (2) block diagram av cc avrh av ss mpx an0 an1 an2 an3 atg f adcr adcs r | b u s internal voltage generator a/d control register trigger start tim0 (internal connection) (reload timer ch2) (peripheral clock) operating clock prescaler input circuit decoder data register successive approxi- mation register comparator sample & hold circuit timer start MB91107/108 50 9. interrupt controller the interrupt controller processes interrupt acknowledgments and arbitration between interrupts. ?hardware configuration this module consists of the following components: ? icr register ? interrupt priority evaluation circuit ? interrupt level/interrupt number (vector) generator ? hold request cancel request generator ?main features the major functions of this module are listed below: ? nmi request/interrupt request detection ? priority evaluation (interrupt level and number) ? transfer of interrupt level as evaluation factor (to the cpu) ? transfer of interrupt number as evaluation factor (to the cpu) ? instruction of returning from the stop mode by nmi/interrupt generation ? generating a request to cancel the hold request to the bus master MB91107/108 51 (1) register configuration ? interrupt control register 0 to 47 address bit 7 bit 0 initial value access address bit 7 bit 0 initial value access 000400 h icr00 - - - 11111 b r/w 000419 h icr25 - - - 11111 b r/w 000401 h icr01 - - - 11111 b r/w 00041a h icr26 - - - 11111 b r/w 000402 h icr02 - - - 11111 b r/w 00041b h icr27 - - - 11111 b r/w 000403 h icr03 - - - 11111 b r/w 00041c h icr28 - - - 11111 b r/w 000404 h icr04 - - - 11111 b r/w 00041d h icr29 - - - 11111 b r/w 000405 h icr05 - - - 11111 b r/w 00041e h icr30 - - - 11111 b r/w 000406 h icr06 - - - 11111 b r/w 00041f h icr31 - - - 11111 b r/w 000407 h icr07 - - - 11111 b r/w 000420 h icr32 - - - 11111 b r/w 000408 h icr08 - - - 11111 b r/w 000421 h icr33 - - - 11111 b r/w 000409 h icr09 - - - 11111 b r/w 000422 h icr34 - - - 11111 b r/w 00040a h icr10 - - - 11111 b r/w 000423 h icr35 - - - 11111 b r/w 00040b h icr11 - - - 11111 b r/w 000424 h icr36 - - - 11111 b r/w 00040c h icr12 - - - 11111 b r/w 000425 h icr37 - - - 11111 b r/w 00040d h icr13 - - - 11111 b r/w 000426 h icr38 - - - 11111 b r/w 00040e h icr14 - - - 11111 b r/w 000427 h icr39 - - - 11111 b r/w 00040f h icr15 - - - 11111 b r/w 000428 h icr40 - - - 11111 b r/w 000410 h icr16 - - - 11111 b r/w 000429 h icr41 - - - 11111 b r/w 000411 h icr17 - - - 11111 b r/w 00042a h icr42 - - - 11111 b r/w 000412 h icr18 - - - 11111 b r/w 00042b h icr43 - - - 11111 b r/w 000413 h icr19 - - - 11111 b r/w 00042c h icr44 - - - 11111 b r/w 000414 h icr20 - - - 11111 b r/w 00042d h icr45 - - - 11111 b r/w 000415 h icr21 - - - 11111 b r/w 00042e h icr46 - - - 11111 b r/w 000416 h icr22 - - - 11111 b r/w 00042f h icr47 - - - 11111 b r/w 000417 h icr23 - - - 11111 b r/w 000418 h icr24 - - - 11111 b r/w ?request level register for canceling hold request address bit 7 bit 0 initial value access 00000431 h hrcl - - - 11111 b r/w r/w : readable and writable - : unused MB91107/108 52 (2) block diagram *1 : dly i stands for delayed interrupt module (delayed interrupt generation block) (refer to the section 11. delayed interrupt module for detail). *2 : int0 is a wake-up signal to clock control block in the sleep or stop status. *3 : hldcan is a bus release request signal for bus masters other than cpu. *4 : level 4 to level 0 are interrupt level outputs. *5 : vct5 to vct0 are interrupt vector outputs. int0 * 2 or nmi ri00 ri47 (dlyirq) dlyi * 1 4 5 6 level 4 ~ 0 * 4 hldcan * 3 vct5 ~ 0 * 5 r-bus im icr00 icr47 priority judgment nmi processing level judgment vector judgment level, vector generation hldreq cancel request MB91107/108 53 10. external interrupt/nmi control block the external interrupt/nmi control block controls external interrupt request signals input to nmi pin and int0 to int7 pins. detecting levels can be selected from h, l, rising edge and falling edge (not for nmi pin). (1) register configuration (2) block diagram ?interrupt enable register address bit 15 bit 8 bit 7 bit 0 initial value access 000095 h eirr enir 00000000 b r/w ?external interrupt cause register bit 15 bit 8 bit 7 bit 0 000094 h eirr enir 00000000 b r/w ?request level setting register bit 15 bit 8 bit 7 bit 0 000099 h eirr enir 00000000 b r/w 9 9 int0 ~ int7 nmi 8 8 8 r bus interrupt request interrupt enable register gate cause f/ request level setting register interrupt cause register edge detection circuit MB91107/108 54 11. delayed interrupt module delayed interrupt module is a module which generates a interrupt for changing a task. by using this delayed interrupt module, an interrupt request to cpu can be generated/cancelled by the software. refer to the section 9. interrupt controller for delayed interrupt module block diagram. ? register configuration ? delayed interrupt control register address bit 7 bit 0 initial value access 000430 h dicr - - - - - - - 0 b r/w r/w : readable and writable - : unused MB91107/108 55 12. clock generation (low-power consumption mechanism) the clock control block is a module which undertakes the following functions. ? cpu clock generation (including gear function) ? peripheral clock generation (including gear function) ? reset generation and cause hold ? standby function (including hardware standby) ? dma request prohibit ? pll (multiplier circuit) embedded (1) register configuration ?reset cause register/watchdog cycle control register address bit 15 bit 10 bit 8 bit 0 initial value access 000480 h rsrr wtcr (stcr) 1xxxx - 0 0 b r/w ?stand-by controled register address bit 15 bit 10 bit 8 bit 0 initial value 000481 h (rsrr/wtcr) stcr 0 0 0 111 - - b r/w ?dma controlerrequest prohibit resister address bit 15 bit 8 bit 0 initial value 000482 h pdrr (ctbr) - - - - 0 0 0 0 b r/w ?timebase timer clear resister address bit 15 bit 8 bit 0 initial value 000483 h pdrr (ctbr) xxxxxxxx b w ?gear control resister address bit 15 bit 8 bit 0 initial value 000484 h gcr (wpr) - - - - 0 0 0 0 b r/w ?watchdog reset generation postpone resister address bit 15 bit 8 bit 0 initial value 000485 h (gcr) wpr xxxxxxxx b w ?pll control resister address bit 15 bit 8 bit 0 initial value 000488 h pctr vacancy 0 0 - - 0 - - - b w r/w : readable and writable w : write only - : unused x : indeterminate MB91107/108 56 (2) block diagram x0 x1 pll 1/2 r | b u s internal reset cpu hold enable dma request power on cell rst pin gcr register cpu gear status transition control circuit pdrr register (watchdog control section) timebase timer cpu clock internal bus clock external bus clock internal bus peripheral clock stop state sleep state cpu hold request hst pin gear control block peripheral gear peripheral dma clock pctr register stcr register count clock watchdog f/f (reset cause circuit) (dna prohibit circuit) rsrr register wpr register ctbr register internal interrupt oscil- lator selection circuit (stop/sleep control section) reset generation f/f internal clock generator circuit internal reset MB91107/108 57 13. external bus interface the external bus interface controls the interface between the device and the external memory and also the external i/o, and has the following features. ? 25-bit (32 mbytes) address output ? 6 independent banks owing to the chip select function. can be set to anywhere on the logical address space for minimum unit 64 kbytes. total 32 mbytes 6 area setting is available by the address pin and the chip select pin. ? 8/16-bit bus width setting are available for every chip select area. areas 6 and 7 allow the inclusive areas to be set. ? programmable automatic memory wait (max. for 7 cycles) can be inserted. ? dram interface support ? three kinds of dram interface: double cas dram (normally dram i/f) single cas dram hyper dram ? 2 banks independent control (ras, cas, etc. control signals) ? dram select is available from 2cas/1we and 1cas/2we. ? hi-speed page mode supported ? cbr/self refresh supported ? programmable wave form ? unused address/data pin can be used for i/o port. ? little endian mode supported ? clock doubler: internal bus 50 mhz, external bus 25 mhz (1) register configuration (continued) ?area selection resister 1 to 5 address bit 15 bit 0 initial value access 00060c h asr1 0 0 0 0 0 0 0 0 b 0 0 0 0 0 0 0 1 b w 000610 h asr2 0 0 0 0 0 0 0 0 b 0 0 0 0 0 0 1 0 b w 000614 h asr3 0 0 0 0 0 0 0 0 b 0 0 0 0 0 0 1 1 b w 000618 h asr4 0 0 0 0 0 0 0 0 b 0 0 0 0 0 1 0 0 b w 00061c h asr5 0 0 0 0 0 0 0 0 b 0 0 0 0 0 1 0 1 b w ?area mask resister 1 to 5 address bit 15 bit 0 initial value 00060e h amr1 0 0 0 0 0 0 0 0 b 0 0 0 0 0 0 0 0 b w 000612 h amr2 0 0 0 0 0 0 0 0 b 0 0 0 0 0 0 0 0 b w 000616 h amr3 0 0 0 0 0 0 0 0 b 0 0 0 0 0 0 0 0 b w 00061a h amr4 0 0 0 0 0 0 0 0 b 0 0 0 0 0 0 0 0 b w 00061e h amr5 0 0 0 0 0 0 0 0 b 0 0 0 0 0 0 0 0 b w MB91107/108 58 (continued) ?area mode resister 0, 1, 32, 4, 5 address bit 15 bit 8 bit 7 bit 0 initial value access amd0 amd1 : 000620 h : 000621 h amd0 amd1 - - - 0 0 1 1 1 b 0 - - 0 0 0 0 0 b r/w amd32 amd4 : 000622 h : 000023 h amd32 amd4 0 0 0 0 0 0 0 0 b 0 - - 0 0 0 0 0 b r/w amd5 : 000624 h amd5 (dscr) 0 - - 0 0 0 0 0 b r/w ?dram signal control resister address bit 15 bit 8 bit 7 bit 0 initial value 000625 h amd5 dscr 0 0 0 0 0 0 0 0 b w ?refresh control resister address bit 15 bit 0 initial value 000626 h rfcr - - xxxxxx b r/w 0 0 - - - 0 0 0 b ?external pin control resister address bit 15 bit 0 initial value 000628 h epcr0 - - - - 1 1 0 0 b - 1 1 1 1 1 1 1 b w 00062a h epcr1 - - - - - - - 1 b 1 1 1 1 1 1 1 1 b w ?dram control resister 4, 5 address bit 15 bit 0 initial value 00062c h dmcr4 0 0 0 0 0 0 0 0 b 0 0 0 0 0 0 0 - b r/w 00062e h dmcr5 0 0 0 0 0 0 0 0 b 0 0 0 0 0 0 0 - b r/w ?little endian resister address bit 15 bit 8 bit 7 bit 0 initial value 0007fe h ler (modr) - - - - - 0 0 0 b w ?mode resister address bit 15 bit 8 bit 7 bit 0 initial value 0007ff h (modr) ler xxxxxxxx b w r/w : readable and writable w : write only - : unused x : indeterminate MB91107/108 59 (2) block diagram a-out mux inpage cs0 ~ cs7 ras0, ras1 cs0l, cs1l cs0h, cs1h dw0, dw1 rd wr0, wr1 brq bgrnt clk rdy 32 32 address bus data bus write buffer read buffer switch switch external data bus + 1or + 2 address buffer asr amr shifter comparator data block address block external address bus dram control underflow dmcr from tbt refresh counter registers & control all blocks control external pin control block MB91107/108 60 n electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) *1 : v cc must not be less than v ss C 0.3 v. *2 : make sure that the voltage does not exceed v cc + 0.3 v, such as when turning on the device. *3 : maximum output current is a peak current value measured at a corresponding pin. *4 : average output current is an average current for a 100 ms period at a corresponding pin. *5 : average total output current is an average current for a 100 ms period for all corresponding pins. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol value unit remarks min. max. power supply voltage v cc v ss - 0.3 v ss + 4.0 v *1 analog supply voltage av cc v ss - 0.3 v ss + 4.0 v *2 analog reference voltage avrh v ss - 0.3 v ss + 4.0 v *2 input voltage v i v ss - 0.3 v cc + 0.3 v analog pin input voltage v ia v ss - 0.3 av cc + 0.3 v output voltage v o v ss - 0.3 v cc + 0.3 v l level maximum output current i ol ? 10 ma *3 l level average output current i olav ? 8ma*4 l level total maximum output current s i ol ? 100 ma l level total average output current s i olav ? 50 ma *5 h level maximum output current i oh ?- 10 ma *3 h level average output current i ohav ?- 4ma*4 h level total maximum output current s i oh ?- 50 ma h level total average output current s i ohav ?- 20 ma *5 power consumption p d ? 500 mw operating temperature t a 0 + 70 c storage temperature tstg - 55 + 150 c MB91107/108 61 2. recommended operating conditions (av ss = v ss = 0.0 v) warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min. max. power supply voltage v cc 3.0 3.6 v normal operation v cc 3.0 3.6 retaining the ram state in stop mode analog supply voltage av cc v ss - 0.3 v ss + 3.6 v analog reference voltage avrh av ss av cc v operating temperature t a 0 + 70 c MB91107/108 62 3. dc characteristics (v cc = 3.0 v to 3.6 v, av ss = v ss = 0.0 v, t a = 0 c to + 70 c) * 1 : hysteresis input pin : nmi , rst , p40 to p47, p50 to p57, p60 to p67, p70, p81, p85, pa1 to pa 6 , p b 0 to pb7, pe0 to pe7, pf0 to pf7, pg0 to pg7, ph0 to ph7, pi0, pi1 *2 : the mb91v107 (development model) has larger supply current than the production models because it contains an development tool interface circuit. parameter symbol pin name condition value unit remarks min. typ. max. h level input voltage v ih input pin ex- cept for hys- teresis input ? 0.7 v cc ? v cc + 0.3 v l level input voltage v ihs *1 0.8 v cc ? v cc + 0.3 v hysteresis input v il input pin ex- cept for hys- teresis input v ss - 0.3 ? 0.25 v cc v v ils *1 v ss - 0.3 ? 0.2 v cc v hysteresis input h level output voltage v oh all output pins v cc = 3.0 v i oh = - 4.0 ma v cc - 0.5 ?? v l level output voltage v ol all output pins v cc = 3.0 v i ol = 8.0 ma ?? 0.4 v input leak current (hi-z out- put leak current) i li all output pins v cc = 3.6 v 0.45 v MB91107/108 64 (1) clock timings (v cc = 3.0 v to 3.6 v, av ss = v ss = 0.0 v, t a = 0 c to + 70 c) *1 : frequency shift ratio stands for deviation ratio of the operating clock from the center frequency in the clock multiplication system. *2 : these values are for a minimum clock of 10 mhz input to x0, a divide-by-2 system of the source oscillation and a 1/8 gear. parameter sym- bol pin name condition value unit remarks min. max. clock frequency (1) f c x0 x1 ? 12.5 12.5 mhz self-oscillation 12.5 mhz internal operation at 50 mhz (using pll, 4 multiplication) clock cycle time t c x0 x1 ? 80 ns frequency shift ratio * 1 (when locked) d f ?? 5 % clock frequency (2) f c x0 x1 ? 10 25 mhz self-oscillation (divide-by-2 input) clock frequency (3) f c x0 x1 10 25 mhz external clock (divide-by-2 input) clock cycle time t c x0 x1 40 100 ns input clock pulse width p wh p wl x0 x1 12.5 to 25 mhz 20 ? ns input to x0, x1 p wh x0 less than 12.5 mh 25 ? ns input to x0 only input clock rising/falling time t cr t cf x0 x1 ?? 8ns (t cr + t cf ) internal operating clock frequency f cp ? ? 0.625 2 50 mhz cpu system f cpp ? 0.625 2 25 mhz peripheral system internal operating clock cycle time t cp ? 20 1600* 2 ns cpu system t cpp ? 40 1600* 2 ns peripheral system d f = 100 ( % ) a f 0 f 0 +a -a + - center frequency MB91107/108 65 050 25 (mhz) 50 12.5 0 0 25 f c (mhz) 0.625 3.6 3.0 (v) f cp / f cpp (mhz) 5 f cp f cp / f cpp v cc 25 10 f cpp cpu 0.8 v cc 0.2 v cc t cf t cr t c p wh p wl clock timing rating measurement conditions operation warranty range external / internal clock setting range power supply internal clock normal operation warranty range (t a = 0 c to +70 c). net masked area are f cpp . max. internal clock frequency setting ll system (12.5 mhz / 4 multiplication) peripheral divide-by-2 system external clock self-oscillation note: when using pll, the external clock must be used need 12.5 mhz. pll oscillation stabilizing period > 100 m s the setting of internal clock must be within above ranges. general oscillation input clock MB91107/108 66 (2) clock output timing (v cc = 3.0 v to 3.6 v, av ss = v ss = 0.0 v, t a = 0 c to + 70 c) *1 : t cyc is a frequency for 1 clock cycle including a gear cycle. *2 : rating at a gear cycle of 1. when a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n in the following equations with 1/2, 1/4, 1/8, respectively. min. : (1 C n/2) t cyc C 10 max. : (1 C n/2) t cyc + 10 select a gear cycle of 1 when using the doubler. *3 : rating at a gear cycle of 1. when a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n in the following equations with 1/2, 1/4, 1/8, respectively. min.: n/2 t cyc C 10 max.: n/2 t cyc + 10 select a gear cycle of 1 when using the doubler. parameter symbol pin name condi- tion value unit remarks min. max. cycle time t cyc clk ? t cp ? ns *1 2 t cp ? using the doubler clk -? clk t chcl clk 1 / 2 t cyc - 10 1 / 2 t cyc + 10 ns *2 clk ? clk - t clch clk 1 / 2 t cyc - 10 1 / 2 t cyc + 10 ns *3 clk v oh v ol v oh t cyc t clch t chcl MB91107/108 67 the relation between source oscillation input and clk pin for configured by chc/cck1/cck0 settings of gcr (gear control register) is as follows. however, in this chart source oscillation input means x0 input clock. t cyc t cyc t cyc t cyc t cyc t cyc source oscillation input (when using the dou- blure) pll system (chc bit of gcr set to 0) (a) gear 1 clk pin cck1/0 : 00 source oscillation input 2 dividing system (chc bit of gcr set to 1) (a) gear 1 clk pin cck1/0 : 00 (b) gear 1/2 clk pin cck1/0 : 01 (c) gear 1/4 clk pin cck1/0 : 10 (d) gear 1/8 clk pin cck1/0 : 11 MB91107/108 68 (3) reset input ratings (v cc = 3.0 v to 3.6 v, av ss = v ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min. max. reset input time t rstl rst ? t cp 5 ? ns rst 0.2 v cc t rstl MB91107/108 69 (4) power-on reset (v cc = 3.0 v to 3.6 v, av ss = v ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min. max. power supply rising time t r v cc v cc = 3.3 v ? 18 ms v cc < 0.2 v before the power supply rising power supply shut off time t off v cc ? 1 ? ms repeated opera- tions oscillation stabilizing time t osc ?? 2 t c 2 20 + 100 m s ? ns 0.2 v t r 0.9 v cc v cc v ss v cc rst v cc t off t osc t rstl notes 1) sudden change in supply voltage during operation may initiate a power-on sequence. to change supply volt- age during operation, it is recommended to smoothly raise the voltage to avoid rapid fluctuations in the supply voltage. a voltage rising rate of 50 mv/ ms or less is recommended. (oscillation stabilizing 2) set rst pin to l level when turning on the device, at least the t rstl duration after the supply voltage reaches v cc is necessary before turning the rst to h level. not less than 3 v 3) if the supply voltage goes below the lower limit of the guaranteed operating voltage range, be sure to restart the power supply from the v ss level. this is because an internal power-on reset must be generated to restart operation without allowing the internal circuit to run out of control. the guaranteed operating voltage range of MB91107 is from 3.0 to 3.6 v. MB91107/108 70 (5) normal bus access read/write operation (v cc = 3.0 v to 3.6 v, av ss = v ss = 0.0 v, t a = 0 c to + 70 c) *1: when bus timing is delayed by automatic wait insertion or rdy input, add (t cyc extended cycle number for delay) to this rating. *2: rating at a gear cycle of 1. when a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n in the following equation with 1/2, 1/4, 1/8, respectively. equation: (2 C n/2) t cyc C 25 parameter sym- bol pin name condi- tion value unit remarks min. max. cs0 to cs7 delay time t chcsl clk cs0 to cs7 ? ? 15 ns cs0 to cs7 delay time t chcsh ? 15 ns address delay time t chav clk a24 to a00 ? 15 ns data delay time t chdv clk d31 to d16 ? 15 ns rd delay time t clrl clk rd ? 15 ns rd delay time t clrh ? 15 ns wr0 , wr1 delay time t clwl clk wr0 to wr1 ? 15 ns wr0 , wr1 delay time t clwh ? 15 ns valid address ? valid data input time t avdv a24 to a00 d31 to d16 ? 3 / 2 t cyc - 25 ns *1 *2 rd ? valid data input time t rldv rd d31 to d16 ? t cyc - 10 ns *1 data set up ? rd - time t dsrh 10 ? ns rd -? data hold time t rhdx 0 ? ns MB91107/108 71 2.4 v clk 0.8 v 2.4 v 0.8 v ba2 2.4 v 0.8 v 2.4 v 0.8 v t clrl 0.8 v t clwl 0.8 v t chdv 0.8 v 2.4 v 0.8 v 2.4 v t clrh 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v t dsrh t rhdx t clwh 2.4 v 2.4 v 0.8 v t chcsh 2.4 v cs0 ~ cs7 a24 ~ a00 rd d31 ~ d16 wr0 ~ wr1 d31 ~ d16 ba1 t cyc t chcsl t rldv t avdv t chav read write MB91107/108 72 (6) ready input timing (v cc = 3.0 v to 3.6 v, av ss = v ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min. max. rdy set up time ? clk t rdys rdy clk ? 15 ? ns clk ? rdy hold time t rdyh clk rdy 0 ? ns clk 2.4 v 2.4 v 0.8 v 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v t rdyh t rdyh rdy rdy t cyc t rdys t rdys (when wait is inserted.) (when no wait is inserted.) MB91107/108 73 (7) hold timing (v cc = 3.0 v to 3.6 v, av ss = v ss = 0.0 v, t a = 0 c to + 70 c) note : there is a delay time of more than 1 cycle from brq input to bgrnt change. parameter symbol pin name condi- tion value unit remarks min. max. bgrnt delay time t chbgl clk bgrnt ? ? 6ns bgrnt delay time t chbgh ? 6ns pin floating ? bgrnt time t xhal bgrnt t cyc - 10 t cyc + 10 ns bgrnt -? pin valid time t hahv t cyc - 10 t cyc + 10 ns clk 2.4 v t chbgl 0.8 v 2.4 v 2.4 v 2.4 v 2.4 v t chbgh brq bgrnt t cyc t hahv t xhal each pin high impedance MB91107/108 74 (8) normal dram mode read/write cycle (v cc = 3.0 v to 3.6 v, av ss = v ss = 0.0 v, t a = 0 c to + 70 c) *1 : when q1 cycle or q4 cycle is extended for 1 cycle, add t cyc time to this rating. *2 : rating at a gear cycle of 1. when a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n in the following equation with 1/2, 1/4, 1/8, respectively. equation: (3 C n/2) t cyc C 16 parameter symbol pin name condi- tion value unit remarks min. max. ras delay time t clrah clk ras ? ? 15 ns ras delay time t chral ? 15 ns cas delay time t clcasl clk cas ? 15 ns cas delay time t clcash ? 15 ns row address delay time t chrav clk a24 to a00 ? 15 ns column address delay time t chcav ? 15 ns dw delay time t chdwl clk dw ? 15 ns dw delay time t chdwh ? 15 ns output data delay time t chdv1 clk d31 to d16 ? 15 ns ras ? valid data input time t rldv ras d31 to d16 ? 5 / 2 t cyc - 16 ns *1 *2 cas ? valid data input time t cldv cas d31 to d16 ? t cyc - 17 ns *1 cas -? data hold time t cadh 0 ? ns MB91107/108 75 0.8 v 2.4 v 0.8 v 2.4 v d31 to d16 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 2.4 v clk 0.8 v q2 q1 q3 q4 q5 2.4 v 2.4 v 0.8 v 0.8 v 0.8 v 2.4 v t chral 0.8 v t clcasl 2.4 v t chrav 0.8 v 2.4 v 0.8 v 2.4 v t cadh 0.8 v 2.4 v t chdwl t chdwh t chdv1 d31 to d16 ras cas a24 to a00 dw t cyc t clrah t chcav t clcash t rldv t cldv 0.8 v 2.4 v row address column address read write MB91107/108 76 (9) normal dram mode fast page read/write cycle (v cc = 3.0 v to 3.6 v, av ss = v ss = 0.0 v, t a = 0 c to + 70 c) * : when q4 cycle is extended for 1 cycle, add t cyc time to this rating. parameter symbol pin name condi- tion value unit remarks min. max. ras delay time t clrah clk, ras ? ? 15 ns cas delay time t clcasl clk cas ? 15 ns cas delay time t clcash ? 15 ns column address delay time t chcav clk a24 to a00 ? 15 ns dw delay time t chdwh clk, dw ? 15 ns output data delay time t chdv1 clk d31 to d16 ? 15 ns cas ? valid data input time t cldv cas d31 to d16 ? t cyc - 17 ns * cas -? data hold time t cadh 0 ? ns MB91107/108 77 0.8 v 2.4 v 0.8 v 2.4 v t clcash 0.8 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v t chdwh t chdv1 0.8 v 2.4 v d31 to d16 clk d31 to d16 ras cas a24 to a00 dw q4 q5 2.4 v 0.8 v q5 0.8 v q4 q5 2.4 v 0.8 v t clrah 2.4 v 2.4 v 0.8 v t clcasl 0.8 v 2.4 v t cadh t chcav t cldv column address column address column address read read read write write MB91107/108 78 (10) single dram timing (v cc = 3.0 v to 3.6 v, av ss = v ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condi- tion value unit remarks min. max. ras delay time t clrah2 clk ras ? ? 15 ns ras delay time t chral2 ? 15 ns cas delay time t chcasl2 clk cas ? n / 2 t cyc + t chcash2 ns cas delay time t chcash2 ? 15 ns row address delay time t chrav2 clk a24 to a00 ? 15 ns column address delay time t chcav2 ? 15 ns dw delay time t chdwl2 clk dw ? 15 ns dw delay time t chdwh2 ? 15 ns output data delay time t chdv2 clk, d31 to d16 ? 15 ns cas ? valid data input time t cldv2 cas d31 to d16 ? (1 - n / 2) t cyc - 17 ns cas -? data hold time t cadh2 0 ? ns MB91107/108 79 column-2 t chcash2 t chral2 t chdwh2 t chdwl2 t chdv2 t chdv2 d31 to d16 clk d31 to d16 ras cas a24 to a00 dw q2 q3 2.4 v 2.4 v 2.4 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 0.8 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v q1 q4s q4s q4s t cadh2 t cldv2 t chrav2 t chcav2 t chcasl2 t cyc 2.4 v 2.4 v t clrah2 2.4 v 2.4 v 0.8 v 0.8 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v column-0 column-1 * 2 * 1 (read) (read) (write) row address read -0 read -1 read -2 write-0 write-1 write-2 *1 : q4s indicates q4sr (read) of single dram cycle or q4sw (write) cycle. *2 : indicates the timing when the bus cycle begins from the high speed page mode. MB91107/108 80 (11) hyper dram timing (v cc = 3.0 v to 3.6 v, av ss = v ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condi- tion value unit remarks min. max. ras delay time t clrah3 clk ras ? ? 15 ns ras delay time t chral3 ? 15 ns cas delay time t chcasl3 clk cas ? n / 2 t cyc + t chcash3 ns cas delay time t chcash3 ? 15 ns row address delay time t chrav3 clk a24 to a00 ? 15 ns column address delay time t chcav3 ? 15 ns rd delay time t chrl3 clk rd ? 15 ns rd delay time t chrh3 ? 15 ns rd delay time t clrl3 ? 15 ns dw delay time t chdwl3 clk dw ? 15 ns dw delay time t chdwh3 ? 15 ns output data delay time t chdv3 clk d31 to d16 ? 15 ns cas ? valid data input time t cldv3 cas d31 to d16 ? t cyc - 17 ns cas ? data hold time t cadh3 0 ? ns MB91107/108 81 t chcash3 t chral3 t chdwh3 t chdwl3 t chdv3 t chdv3 d31 to d16 clk d31 to d16 ras cas rd a24 to a00 dw q2 q3 2.4 v 2.4 v 2.4 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 0.8 v 0.8 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v q1 q4h q4h q4h 0.8 v t cadh3 t cldv3 t chrav3 t clrl3 0.8 v t chrl3 t chcasl3 t cyc 2.4 v t clrah3 2.4 v 2.4 v 0.8 v 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v column-0 column-1 * 2 * 2 * 1 column-2 t chrh3 t chcav3 0.8 v 2.4 v 0.8 v 0.8 v (read) (read) (read) (write) row address read -0 read -1 write-0 write-1 write-2 *1 : q4s indicates q4hr (read) of single dram cycle or q4hw (write) cycle. *2 : indicates the timing when the bus cycle begins from the high speed page mode. MB91107/108 82 (12) cbr refresh (v cc = 3.0 v to 3.6 v, av ss = v ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condi- tion value unit remarks min. max. ras delay time t clrah clk ras ? ? 15 ns ras delay time t chral ? 15 ns cas delay time t clcasl clk cas ? 15 ns cas delay time t clcash ? 15 ns t clcash clk ras cas 0.8 v 0.8 v r4 2.4 v 0.8 v t clrah r3 r2 r1 0.8 v 2.4 v 2.4 v 2.4 v 0.8 v t chral t clcasl dw t cyc MB91107/108 83 (13) self refresh (v cc = 3.0 v to 3.6 v, av ss = v ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condi- tion value unit remarks min. max. ras delay time t clrah clk ras ? ? 15 ns ras delay time t chral ? 15 ns cas delay time t clcasl clk cas ? 15 ns cas delay time t clcash ? 15 ns clk ras cas 0.8 v t chral sr1 2.4 v t chcasl t clrah 2.4 v sr2 2.4 v sr3 0.8 v 0.8 v sr3 0.8 v 2.4 v 2.4 v t clcash t cyc MB91107/108 84 (14) uart timing (v cc = 3.0 v to 3.6 v, av ss = v ss = 0.0 v, t a = 0 c to + 70 c) notes: ? this rating is for ac characteristics in clk synchronous mode. ? t cycp : a cycle time of peripheral system clock parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc ? internal shift clock mode 8 t cycp ? ns sclk ? sout delay time t slov ?- 80 80 ns valid sin ? sclk - t ivsh ? 100 ? ns sclk -? valid sin hold time t shix ? 60 ? ns serial clock h pulse width t shsl ? external shift clock mode 4 t cycp ? ns serial clock l pulse width t slsh ? 4 t cycp ? ns sclk ? sout delay time t slov ?? 150 ns valid sin ? sclk - t ivsh ? 60 ? ns sclk -? valid sin hold time t shix ? 60 ? ns MB91107/108 85 sclk sout sin sclk sout sin t scyc t slov t ivsh t shix t slov t slsh t shsl t ivsh t shix 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc internal shift clock mode external shift clock mode MB91107/108 86 (15) trigger system input timing to (v cc = 3.0 v to 3.6 v, av ss = v ss = 0.0 v, t a = 0 c to + 70 c) note : t cycp : a cycle time of peripheral system clock parameter symbol pin name condi- tion value unit remarks min. max. a/d start trigger input time t atgx atg ? 5 t cycp ? ns ppg start trigger input time t ptgr trg0 to trg3 ? 5 t cycp ? ns atg trg0 to trg3 t atgx 0.2 v cc MB91107/108 87 (16) dma controller timing (v cc = 3.0 v to 3.6 v, av ss = v ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condi- tion value unit remarks min. max. dreq input pulse width t drwh dreq0 to dreq2 ? 2 t cyc ? ns dack delay time (normal bus) (normal dram) t cldl clk dack0 to dack2 ? 6ns t cldh ? 6ns eop delay time (normal bus) (normal dram) t clel clk eop0 to eop2 ? 6ns t cleh ? 6ns dack delay time (single dram) (hyper dram) t chdl clk dack0 to dack2 ? n / 2 t cyc ns t chdh ? 6ns eop delay time (single dram) (hyper dram) t chel clk eop0 to eop2 ? n / 2 t cyc ns t cheh ? 6ns clk dreq0 to dreq2 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 0.8 v 0.8 v 0.8 v 2.4 v 2.4 v dack0 to dack2 eop0 to eop2 dack0 to dack2 eop0 to eop2 (single dram) (hyper dram) t cyc t drwh t cldl t clel t chdl t chel t cldh t cleh t chdh t cheh (normal bus) (normal dram) MB91107/108 88 5. a/d converter block electrical characteristics (av cc = v cc = + 3.0 v to + 3.6 v, av ss = v ss = 0.0 v, avrh = + 3.0 v to + 3.6 v, t a = 0 c to + 70 c) *1: av cc = v cc = 3.0 v to 3.6 v(for a machine clock of 25 mhz). *2: current value for a/d converters not in operation, cpu stop mode (v cc = av cc = avrh = 3.6 v) notes: ? as the absolute value of avrh decreases, relative error increases. ? output impedance of external circuit of analog input under following conditions; output impedance of external circuit < 7 k w . if output impedance of external circuit is too high, analog voltage sampling time may be too short for accurate sampling. parameter symbol pin name value unit min. typ. max. resolution ?? ? 10 10 bit total error ?? ? ? 4.0 lsb linearity error ?? ? ? 3.0 lsb differentiation linearity error ?? ? ? 2.5 lsb zero transition voltage v ot an0 to an3 - 1.5 + 0.5 + 2.5 lsb full-scale transition voltage v fst an0 to an3 avrh - 4.5 avrh - 1.5 avrh + 0.5 lsb conversion time ?? 5.6* 1 ??m s analog port input current i ain an0 to an3 ? 0.1 10 m a analog input voltage v ain an0 to an3 av ss ? avrh v reference voltage ? avrh av ss ? av cc v power supply current i a av cc ? 500 ?m a i ah ?? 5* 2 m a reference voltage supply current i r avrh ? 500 ?m a i rh ?? 5* 2 m a conversion variance between channels ? an0 to an3 ?? 4lsb analog input circuit model plan r on1 : 5 k w r on2 : 620 w r on3 : 620 w r on4 : 480 w c 0 : 2 pf c 1 : 2 pf r on1 r on2 r on3 r on4 c 0 c 1 sample and hold circuit analog input comparator note: listed values are for reference purposes only. r onx , c x are preliminary value. MB91107/108 89 6. a/d converter glossary ? resolution the smallest change in analog voltage detected by a/d converter. ? linearity error a deviation of actual conversion characteristic from a line connecting the zero-traction point (between 00 0000 0000 ? 00 0000 0001) to the full-scale transition point (between 11 1111 1110 ? 11 1111 1111). ? differential linearity error a deviation of a step voltage for changing the lsb of output code from ideal input voltage 3ff 3fe 3fd 004 003 002 001 avrl avrh {1 lsb (n - 1) + v ot } v nt v fst v ot n - 1 avrl avrh n - 2 n n + 1 v nt v (n + 1)t linearity error differential linearity error digital output digital output actual conversion characteristic analog input analog input linearity error of digital output n = v nt - {1 lsb (n - 1) + v ot } 1 lsb [lsb] differential linearity error of digital output n = v ( n + 1 ) t - v nt 1 lsb - 1 1 lsb = v fst - v ot 1022 [v] 1 lsb (ideal value) = avrh - avrl 1024 [v] v ot : a voltage for causing transition of digital output from (000) h to (001) h v fst : a voltage for causing transition of digital output from (3fe) h to (3ff) h v nt : a voltage for causing transition of digital output from (n - 1) to n [lsb] actual conversion characteristic actual conversion characteristic actual conversion character istic (measured value) (measured val ue) (measured value) (measured value) (measured value) ideal val ue ideal valu e MB91107/108 90 ? total error a difference between actual value and theoretical value. the overall error includes zero-transition error, full- scale transition error and linearity error. v nt - {1 lsb (n - 1) + 0.5 lsb} 1 lsb 3ff 3fe 3fd 004 003 002 001 avrl avrh 1.5 lsb v nt 0.5 lsb {1 lsb (n - 1) + 0.5 lsb} total error digital output analog input total error of digital output n = [lsb] v ot (ideal value) = avrl + 0.5 lsb [v] v fst (ideal value) = avrh - 1.5 lsb [v] v nt : a voltage for causing transition of digital output from (n - 1) to n ideal value actual conversion characteristic (measured value) actual conversion characteristic MB91107/108 91 n reference data (1) h level output voltage (2) l level output voltage h level output voltage vs. power supply voltage l level output voltage vs. power supply voltage (3) h level input / l level input voltage (cmos input) (4) hlevel input / l level input voltage (hysteresys input) input level vs. power supply voltage (cmos ) input level vs. power supply voltage (hysteresys ) 4.00 3.80 3.60 3.40 3.20 3.00 2.80 2.60 2.40 2.20 2.00 2.7 3.0 3.3 3.6 3.9 v oh (v) v cc (v) 140.0 135.0 130.0 125.0 120.0 150.0 110.0 105.0 100.0 2.7 3.0 3.3 3.6 3.9 v ol (v) v cc (v) 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 2.7 3.0 3.3 3.6 3.9 v ih v il v cc (v) v in (v) 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 2.7 3.0 3.3 3.6 3.9 v ih v il v cc (v) v in (v) MB91107/108 92 (5) power supply current 100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 2.7 3.0 3.3 3.6 3.9 50 mhz 25 mhz i cc (ma) v cc (v) power supply current vs. voltage 60.0 50.0 40.0 30.0 20.0 10.0 0.0 2.7 3.0 3.3 3.6 3.9 50 mhz 25 mhz i ccs (ma) v cc (v) power supply current (sleep mode) vs. power supply current 100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 2.7 3.0 3.3 3.6 3.9 v cc (v) i cch ( m a) power supply current (stop mode) vs. power supply voltage 450 400 350 300 250 200 150 100 50 0 2.7 3.0 3.3 3.6 3.9 av cc (v) i a ( m a) a/d conversion block power supply current vs. power supply voltage (25 mhz) 300 280 260 240 220 200 180 160 2.7 3.0 3.3 3.6 3.9 avrh (v) i r ( m a) a / d conversion block reference voltage supply current vs. voltage (25 mhz) MB91107/108 93 (6) pull-up / pull-down resistance 100.0 10.0 2.7 3.0 3.3 3.6 3.9 v cc (v) r ( w ) pull-down resistance vs. power supply voltage 100.0 10.0 2.7 3.0 3.3 3.6 3.9 v cc (v) r ( w ) pull-up resistance vs. power supply voltage MB91107/108 94 n instructions (165 instructions) 1. how to read instruction set summary (1) names of instructions instructions marked with * are not included in cpu specifications. these are extended instruction codes added/extended at assembly language levels. (2) addressing modes specified as operands are listed in symbols. refer to 2. addressing mode symbols for further information. (3) instruction types (4) hexa-decimal expressions of instructions (5) the number of machine cycles needed for execution a: memory access cycle and it has possibility of delay by ready function. b: memory access cycle and it has possibility of delay by ready function. if an object register in a ld operation is referenced by an immediately following instruction, the interlock function is activated and number of cycles needed for execution increases. c: if an immediately following instruction operates to an object of r15, ssp or usp in read/write mode or if the instruction belongs to instruction format a group, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. d: if an immediately following instruction refers to mdh/mdl, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. for a, b, c and d, minimum execution cycle is 1. (6) change in flag sign ? flag change c : change C : no change 0:clear 1:set ? flag meanings n : negative flag z:zero flag v:over flag c:carry flag (7) operation carried out by instruction mnemonic type op cyc nzvc operation remarks add rj, ri * add #s5, ri , , a c , , a6 a4 , , 1 1 , , cccc cccc , , ri + rj ? ri ri + s5 ? ri , , (1) (2) (3) (4) (5) (6) (7) MB91107/108 95 2. addressing mode symbols ri : register direct (r0 to r15, ac, fp, sp) rj : register direct (r0 to r15, ac, fp, sp) r13 : register direct (r13, ac) ps : register direct (program status register) rs : register direct (tbr, rp, ssp, usp, mdh, mdl) cri : register direct (cr0 to cr15) crj : register direct (cr0 to cr15) #i8 : unsigned 8-bit immediate (C128 to 255) note: C128 to C1 are interpreted as 128 to 255 #i20 : unsigned 20-bit immediate (C0x80000 to 0xfffff) note: C0x7ffff to C1 are interpreted as 0x7ffff to 0xfffff #i32 : unsigned 32-bit immediate (C0x80000000 to 0xffffffff) note: C0x80000000 to C1 are interpreted as 0x80000000 to 0xffffffff #s5 : signed 5-bit immediate (C16 to 15) #s10 : signed 10-bit immediate (C512 to 508, multiple of 4 only) #u4 : unsigned 4-bit immediate (0 to 15) #u5 : unsigned 5-bit immediate (0 to 31) #u8 : unsigned 8-bit immediate (0 to 255) #u10 : unsigned 10-bit immediate (0 to 1020, multiple of 4 only) @dir8 : unsigned 8-bit direct address (0 to 0xff) @dir9 : unsigned 9-bit direct address (0 to 0x1fe, multiple of 2 only) @dir10 : unsigned 10-bit direct address (0 to 0x3fc, multiple of 4 only) label9 : signed 9-bit branch address (C0x100 to 0xfc, multiple of 2 only) label12 : signed 12-bit branch address (C0x800 to 0x7fc, multiple of 2 only) label20 : signed 20-bit branch address (C0x80000 to 0x7ffff) label32 : signed 32-bit branch address (C0x80000000 to 0x7fffffff) @ri : register indirect (r0 to r15, ac, fp, sp) @rj : register indirect (r0 to r15, ac, fp, sp) @(r13, rj) : register relative indirect (rj: r0 to r15, ac, fp, sp) @(r14, disp10) : register relative indirect (disp10: C0x200 to 0x1fc, multiple of 4 only) @(r14, disp9) : register relative indirect (disp9: C0x100 to 0xfe, multiple of 2 only) @(r14, disp8) : register relative indirect (disp8: C0x80 to 0x7f) @(r15, udisp6) : register relative (udisp6: 0 to 60, multiple of 4 only) @ri+ : register indirect with post-increment (r0 to r15, ac, fp, sp) @r13+ : register indirect with post-increment (r13, ac) @sp+ : stack pop @Csp : stack push (reglist) : register list MB91107/108 96 3. instruction types add, addn, cmp, lsl, lsr and asr instructions only msb ty p e a ri lsb rj op ty p e b ty p e c ty p e * c ty p e d ty p e e ty p e f 16 bits 4 4 8 op i8/o8 ri 484 ri u4/m4 op 4 4 8 op s5/u5 ri 754 op u8/rel8/dir/reglist 88 op sub-op ri 844 op rel11 511 MB91107/108 97 4. detailed description of instructions ? add/subtract operation instructions (10 instructions) ? compare operation instructions (3 instructions) ? logical operation instructions (12 instructions) mnemonic type op cycle n z v c operation remarks add rj, ri * add #s5, ri add #i4, ri add2 #i4, ri a c c c a6 a4 a4 a5 1 1 1 1 cccc cccc cccc cccc ri + rj ? ri ri + s5 ? ri ri + extu (i4) ? ri ri + extu (i4) ? ri msb is interpreted as a sign in assembly language zero-extension sign-extension addc rj, ri a a7 1 cccc ri + rj + c ? ri add operation with sign addn rj, ri * addn #s5, ri addn #i4, ri addn2 #i4, ri a c c c a2 a0 a0 a1 1 1 1 1 CCCC CCCC CCCC CCCC ri + rj ? ri ri + s5 ? ri ri + extu (i4) ? ri ri + extu (i4) ? ri msb is interpreted as a sign in assembly language zero-extension sign-extension sub rj, ri a ac 1 cccc ri C rj ? ri subc rj, ri a ad 1 cccc ri C rj C c ? ri subtract operation with carry subn rj, ri a ae 1 C C C C ri C rj ? ri mnemonic type op cycle n z v c operation remarks cmp rj, ri * cmp #s5, ri cmp #i4, ri cmp2 #i4, ri a c c c aa a8 a8 a9 1 1 1 1 cccc cccc cccc cccc ri C rj ri C s5 ri + extu (i4) ri + extu (i4) msb is interpreted as a sign in assembly language zero-extension sign-extension mnemonic type op cycle n z v c operation remarks and rj, ri and rj, @ri andh rj, @ri andb rj, @ri a a a a 82 84 85 86 1 1 + 2a 1 + 2a 1 + 2a ccC C ccC C ccC C ccC C ri & = rj (ri) & = rj (ri) & = rj (ri) & = rj word word half word byte or rj, ri or rj, @ri orh rj, @ri orb rj, @ri a a a a 92 94 95 96 1 1 + 2a 1 + 2a 1 + 2a ccC C ccC C ccC C ccC C ri | = rj (ri) | = rj (ri) | = rj (ri) | = rj word word half word byte eor rj, ri eor rj, @ri eorh rj, @ri eorb rj, @ri a a a a 9a 9c 9d 9e 1 1 + 2a 1 + 2a 1 + 2a ccC C ccC C ccC C ccC C ri ^ = rj (ri) ^ = rj (ri) ^ = rj (ri) ^ = rj word word half word byte MB91107/108 98 ? bit manipulation arithmetic instructions (8 instructions) *1: assembler generates bandl if result of logical operation u8&0x0f leaves an active (set) bit and generates bandh if u8&0xf0 leaves an active bit. depending on the value in the u8 format, both bandl and bandh may be generated. *2: assembler generates borl if result of logical operation u8&0x0f leaves an active (set) bit and generates borh if u8&0xf0 leaves an active bit. *3: assembler generates beorl if result of logical operation u8&0x0f leaves an active (set) bit and generates beorh if u8&0xf0 leaves an active bit. ? add/subtract operation instructions (10 instructions) *1: divos, div1 32, div2, div3 and div4s are generated. a total instruction code length of 72 bytes. *2: divou and div1 32 are generated. a total instruction code length of 66 bytes. mnemonic type op cycle n z v c operation remarks bandl #u4, @ri (u4: 0 to 0f h ) bandh #u4, @ri (u4: 0 to 0f h ) * band #u8, @ri * 1 c c 80 81 1 + 2a 1 + 2a C CCCC CCCC CCCC (ri) & = (f0 h + u4) (ri) & = ((u4<<4) + 0f h ) (ri) & = u8 manipulate lower 4 bits manipulate upper 4 bits borl #u4, @ri (u4: 0 to 0f h ) borh #u4, @ri (u4: 0 to 0f h ) * bor #u8, @ri * 2 c c 90 91 1 + 2a 1 + 2a C CCCC CCCC CCCC (ri) | = u4 (ri) | = (u4<<4) (ri) | = u8 manipulate lower 4 bits manipulate upper 4 bits beorl #u4, @ri (u4: 0 to 0f h ) beorh #u4, @ri (u4: 0 to 0f h ) * beor #u8, @ri * 3 c c 98 99 1 + 2a 1 + 2a C CCCC CCCC CCCC (ri) ^ = u4 (ri) ^ = (u4<<4) (ri) ^ = u8 manipulate lower 4 bits manipulate upper 4 bits btstl #u4, @ri (u4: 0 to 0f h ) btsth #u4, @ri (u4: 0 to 0f h ) c c 88 89 2 + a 2 + a 0cCC ccC C (ri) & u4 (ri) & (u4<<4) te s t l o w e r 4 b i t s test upper 4 bits mnemonic type op cycle n z v c operation remarks mul rj, ri mulu rj, ri mulh rj, ri muluh rj, ri a a a a af ab bf bb 5 5 3 3 cccC cccC ccC C ccC C rj ri ? mdh, mdl rj ri ? mdh, mdl rj ri ? mdl rj ri ? mdl 32-bit 32-bit = 64-bit unsigned 16-bit 16-bit = 32-bit unsigned divos ri divou ri div1 ri div2 ri div3 div4s * div ri * 1 * divu ri * 2 e e e e e e 97 C 4 97 C 5 97 C 6 97 C 7 9f C 6 9f C 7 1 1 d 1 1 1 C C CCCC CCCC CcCc CcCc CCCC CCCC CcCc CcCc mdl/ri ? mdl, mdl%ri ? mdh mdl/ri ? mdl, mdl%ri ? mdh step calculation 32-bit/32-bit = 32-bit unsigned MB91107/108 99 ? shift arithmetic instructions (9 instructions) ? immediate value data transfer instruction (immediate value set/16-bit/32-bit immediate value transfer instruction) (3 instructions) *1: if an immediate value is given in absolute, assembler automatically makes i8, i20 or i32 selection. if an immediate value contains relative value or external reference, assembler selects i32. ? memory load instructions (13 instructions) notethe relations between o8 field of type-b and u4 field of type-c in the instruction format and assembler description from disp8 to disp10 are as follows: disp8 ? o8 = disp8:each disp is a code extension. disp9 ? o8 = disp9>>1:each disp is a code extension. disp10 ? o8 = disp10>>2:each disp is a code extension. udisp6 ? u4 = udisp6>>2:udisp4 is a 0 extension. mnemonic type op cycle n z v c operation remarks lsl rj, ri * lsl #u5, ri lsl #u4, ri lsl2 #u4, ri a c c c b6 b4 b4 b5 1 1 1 1 ccCc ccCc ccCc ccCc ri< MB91107/108 100 ? memory store instructions (13 instructions) notethe relations between o8 field of type-b and u4 field of type-c in the instruction format and assembler description from disp8 to disp10 are as follows: disp8 ? o8 = disp8:each disp is a code extension. disp9 ? o8 = disp9>>1:each disp is a code extension. disp10 ? o8 = disp10>>2:each disp is a code extension. udisp6 ? u4 = udisp6>>2:udisp4 is a 0 extension. ? transfer instructions between registers/special-purpose registers transfer instructions (5 instructions) mnemonic type op cycle n z v c operation remarks st ri, @rj st ri, @(r13, rj) st ri, @(r14, disp10) st ri, @(r15, udisp6) st ri, @Cr15 st rs, @Cr15 st ps, @Cr15 a a b c e e e 14 10 30 13 17 C 0 17 C 8 17 C 9 a a a a a a a CCCC CCCC CCCC CCCC CCCC CCCC CCCC ri ? (rj) ri ? (r13 + rj) ri ? (r14 + disp10) ri ? (r15 + usidp6) r15 C = 4, ri ? (r15) r15 C = 4, rs ? (r15) r15 C = 4, ps ? (r15) word word word rs: special-purpose register sth ri, @rj sth ri, @(r13, rj) sth ri, @(r14, disp9) a a b 15 11 50 a a a CCCC CCCC CCCC ri ? (rj) ri ? (r13 + rj) ri ? (r14 + disp9) half word half word half word stb ri, @rj stb ri, @(r13, rj) stb ri, @(r14, disp8) a a b 16 12 70 a a a CCCC CCCC CCCC ri ? (rj) ri ? (r13 + rj) ri ? (r14 + disp8) byte byte byte mnemonic type op cycle n z v c operation remarks mov rj, ri mov rs, ri mov ri, rs mov ps, ri mov ri, ps a a a e e 8b b7 b3 17 C 1 07 C 1 1 1 1 1 c CCCC CCCC CCCC CCCC cccc rj ? ri rs ? ri ri ? rs ps ? ri ri ? ps transfer between general-purpose registers rs: special-purpose register rs: special-purpose register MB91107/108 101 ? non-delay normal branch instructions (23 instructions) notes: ? 2/1 in cycle sections indicates that 2 cycles are needed for branch and 1 cycle needed for non-branch. ? the relations between rel8 field of type-d and rel11 field of type-f in the instruction format and assembler discription label9 and label12 are as follows. label9 ? rel8 = (label9 C pc C 2)/2 label12 ? rel11 = (label12 C pc C 2)/2 ? reti must be operated while s flag = 0. mnemonic type op cycle n z v c operation remarks jmp @ri e 97 C 0 2 CCCC ri ? pc call label12 call @ri f e d0 97 C 1 2 2 CCCC CCCC pc + 2 ? rp, pc + 2 + rel11 2 ? pc pc + 2 ? rp, ri ? pc ret e 97 C 2 2 C C C C rp ? pc return int #u8 d 1f 3+3a C C C C ssp C = 4, ps ? (ssp), ssp C = 4, pc + 2 ? (ssp), 0 ? i flag, 0 ? s flag, (tbr + 3fc C u8 4) ? pc inte e 9f C 3 3 + 3a C C C C ssp C = 4, ps ? (ssp), ssp C = 4, pc + 2 ? (ssp), 0 ? s flag, (tbr + 3d8 C u8 4) ? pc for emulator reti e 97 C 3 2 + 2a c c c c (r15) ? pc, r15 C = 4, (r15) ? ps, r15 C = 4 bno label9 bra label9 beq label9 bne label9 bc label9 bnc label9 bn label9 bp label9 bv label9 bnv label9 blt label9 bge label9 ble label9 bgt label9 bls label9 bhi label9 d d d d d d d d d d d d d d d d e1 e0 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef 1 2 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC non-branch pc + 2 + rel8 2 ? pc pcif z = = 1 pcif z = = 0 pcif c = = 1 pcif c = = 0 pcif n = = 1 pcif n = = 0 pcif v = = 1 pcif v = = 0 pcif v xor n = = 1 pcif v xor n = = 0 pcif (v xor n) or z = = 1 pcif (v xor n) or z = = 0 pcif c or z = = 1 pcif c or z = = 0 MB91107/108 102 ? branch instructions with delays (20 instructions) notes: ? the relations between rel8 field of type-d and rel11 field of type-f in the instruction format and assembler discription label9 and label12 are as follows. label9 ? rel8 = (label9 C pc C 2)/2 label12 ? rel11 = (label12 C pc C 2)/2 ? delayed branch operation always executes next instruction (delay slot) before making a branch. ? instructions allowed to be stored in the delay slot must meet one of the following conditions. if the other instruction is stored, this device may operate other operation than defined. the instruction described 1 in the other cycle column than branch instruction. the instruction described a, b, c or d in the cycle column. mnemonic type op cycle n z v c operation remarks jmp:d @ri e 9f C 0 1 CCCC ri ? pc call:d label12 call:d @ri f e d8 9f C 1 1 1 CCCC CCCC pc + 4 ? rp, pc + 2 + rel11 2 ? pc pc + 4 ? rp, ri ? pc ret:d e 9f C 2 1 CCCC rp ? pc return bno:d label9 bra:d label9 beq:d label9 bne:d label9 bc:d label9 bnc:d label9 bn:d label9 bp:d label9 bv:d label9 bnv:d label9 blt:d label9 bge:d label9 ble:d label9 bgt:d label9 bls:d label9 bhi:d label9 d d d d d d d d d d d d d d d d f1 f0 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC non-branch pc + 2 + rel8 2 ? pc pcif z = = 1 pcif z = = 0 pcif c = = 1 pcif c = = 0 pcif n = = 1 pcif n = = 0 pcif v = = 1 pcif v = = 0 pcif v xor n = = 1 pcif v xor n = = 0 pcif (v xor n) or z = = 1 pcif (v xor n) or z = = 0 pcif c or z = = 1 pcif c or z = = 0 MB91107/108 103 ? direct addressing instructions notethe relations between the dir field of type-d in the instruction format and the assembler description from disp8 to disp10 are as follows: disp8 ? dir + disp8:each disp is a code extension disp9 ? dir = disp9>>1:each disp is a code extension disp10 ? dir = disp10>>2:each disp is a code extension ? resource instructions (2 instructions) ? co-processor instructions (4 instructions) mnemonic type op cycle n z v c operation remarks dmov @dir10, r13 dmov r13, @dir10 dmov @dir10, @r13+ dmov @r13+, @dir10 dmov @dir10, @Cr15 dmov @r15+, @dir10 d d d d d d 08 18 0c 1c 0b 1b b a 2a 2a 2a 2a CCCC CCCC CCCC CCCC CCCC CCCC (dir10) ? r13 r13 ? (dir10) (dir10) ? (r13), r13 + = 4 (r13) ? (dir10), r13 + = 4 r15 C = 4, (dir10) ? (r15) (r15) ? (dir10), r15 + = 4 word word word word word word dmovh @dir9, r13 dmovh r13, @dir9 dmovh @dir9, @r13+ dmovh @r13+, @dir9 d d d d 09 19 0d 1d b a 2a 2a CCCC CCCC CCCC CCCC (dir9) ? r13 r13 ? (dir9) (dir9) ? (r13), r13 + = 2 (r13) ? (dir9), r13 + = 2 half word half word half word half word dmovb @dir8, r13 dmovb r13, @dir8 dmovb @dir8, @r13+ dmovb @r13+, @dir8 d d d d 0a 1a 0e 1e b a 2a 2a CCCC CCCC CCCC CCCC (dir8) ? r13 r13 ? (dir8) (dir8) ? (r13), r13 + + (r13) ? (dir8), r13 + + byte byte byte byte mnemonic type op cycle n z v c operation remarks ldres @ri+, #u4 c bc a C C C C (ri) ? u4 resource ri + = 4 u4: channel number stres #u4, @ri+ c bd a C C C C u4 resource ? (ri) ri + = 4 u4: channel number mnemonic type op cycle n z v c operation remarks copop #u4, #cc, crj, cri copld #u4, #cc, rj, cri copst #u4, #cc, crj, ri copsv #u4, #cc, crj, ri e e e e 9f C c 9f C d 9f C e 9f C f 2 + a 1 + 2a 1 + 2a 1 + 2a CCCC CCCC CCCC CCCC calculation rj ? cri crj ? ri crj ? ri no error traps MB91107/108 104 ? other instructions (16 instructions) *1: in the addsp instruction, the reference between u8 of type-d in the instruction format and assembler description s10 is as follows. s10 ? s8 = s10>>2 *2: in the enter instruction, the reference between i8 of type-c in the instruction format and assembler description u10 is as follows. u10 ? u8 = u10>>2 *3: if either of r0 to r7 is specified in reglist, assembler generates ldm0. if either of r8 to r15 is specified, assembler generates ldm1. both ldm0 and ldm1 may be generated. *4: the number of cycles needed for execution of ldm0 (reglist) and ldm1 (reglist) is given by the following calculation; a (n C 1) + b + 1 when n is number of registers specified. *5: if either of r0 to r7 is specified in reglist, assembler generates stm0. if either of r8 to r15 is specified, assembler generates stm1. both stm0 and stm1 may be generated. *6: the number of cycles needed for execution of stm0 (reglist) and stm1 (reglist) is given by the following calculation; a n + 1 when n is number of registers specified. mnemonic type op cycle n z v c operation remarks nop e 9f C a 1 C C C C no changes andccr #u8 orccr #u8 d d 83 93 c c cccc cccc ccr and u8 ? ccr ccr or u8 ? ccr stilm #u8 d 87 1 CCCC i8 ? ilm set ilm immediate value addsp #s10 * 1 d a3 1 CCCC r15 + = s10 add sp instruction extsb ri extub ri extsh ri extuh ri e e e e 97 C 8 97 C 9 97 C a 97 C b 1 1 1 1 CCCC CCCC CCCC CCCC sign extension 8 ? 32 bits zero extension 8 ? 32 bits sign extension 16 ? 32 bits zero extension 16 ? 32 bits ldm0 (reglist) ldm1 (reglist) * ldm (reglist) * 3 d d 8c 8d * 4 * 4 C CCCC CCCC CCCC (r15) ? reglist, r15 increment (r15) ? reglist, r15 increment (r15 + +) ? reglist, load-multi r0 to r7 load-multi r8 to r15 load-multi r0 to r15 stm0 (reglist) stm1 (reglist) * stm2 (reglist) * 5 d d 8e 8f * 6 * 6 C CCCC CCCC CCCC r15 decrement, reglist ? (r15) r15 decrement, reglist ? (r15) reglist ? (r15 + +) store-multi r0 to r7 store-multi r8 to r15 store-multi r0 to r15 enter #u10 * 2 d 0f 1+a CCCC r14 ? (r15 C 4), r15 C 4 ? r14, r15 C u10 ? r15 entrance processing of function leave e 9f C 9 b C C C C r14 + 4 ? r15, (r15 C 4) ? r14 exit processing of function xchb @rj, ri a 8a 2a C C C C ri ? temp, (rj) ? ri, temp ? (rj) for semafo management byte data MB91107/108 105 ? 20-bit normal branch macro instructions *1: call20 (1) if label20 C pc C 2 is between C0x800 and +0x7fe, instruction is generated as follows; call label12 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:20 #label20, ri call @ri *2: bra20 (1) if label20 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bra label9 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:20 #label20, ri jmp @ri *3: bcc20 (beq20 to bhi20) (1) if label20 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bcc label9 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; bxcc false xcc is a revolt condition of cc ldi:20 #label20, ri jmp @ri false: mnemonic operation remarks * call20 label20, ri next instruction address ? rp, label20 ? pc ri: temporary register * 1 * bra20 label20, ri * beq20 label20, ri * bne20 label20, ri * bc20 label20, ri * bnc20 label20, ri * bn20 label20, ri * bp20 label20, ri * bv20 label20, ri * bnv20 label20, ri * blt20 label20, ri * bge20 label20, ri * ble20 label20, ri * bgt20 label20, ri * bls20 label20, ri * bhi20 label20, ri label20 ? pc if (z = = 1) then label20 ? pc ifs/z = = 0 ifs/c = = 1 ifs/c = = 0 ifs/n = = 1 ifs/n = = 0 ifs/v = = 1 ifs/v = = 0 ifs/v xor n = = 1 ifs/v xor n = = 0 ifs/(v xor n) or z = = 1 ifs/(v xor n) or z = = 0 ifs/c or z = = 1 ifs/c or z = = 0 ri: temporary register * 2 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 MB91107/108 106 ? 20-bit delayed branch macro instructions *1: call20:d (1) if label20 C pc C 2 is between C0x800 and +0x7fe, instruction is generated as follows; call:d label12 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:20 #label20, ri call:d @ri *2: bra20:d (1) if label20 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bra:d label9 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:20 #label20, ri jmp:d @ri *3: bcc20:d (beq20:d to bhi20:d) (1) if label20 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bcc:d label9 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; bxcc false xcc is a revolt condition of cc ldi:20 #label20, ri jmp:d @ri false: mnemonic operation remarks * call20:d label20, ri next instruction address + 2 ? rp, label20 ? pc ri: temporary register * 1 * bra20:d label20, ri * beq20:d label20, ri * bne20:d label20, ri * bc20:d label20, ri * bnc20:d label20, ri * bn20:d label20, ri * bp20:d label20, ri * bv20:d label20, ri * bnv20:d label20, ri * blt20:d label20, ri * bge20:d label20, ri * ble20:d label20, ri * bgt20:d label20, ri * bls20:d label20, ri * bhi20:d label20, ri label20 ? pc if (z = = 1) then label20 ? pc ifs/z = = 0 ifs/c = = 1 ifs/c = = 0 ifs/n = = 1 ifs/n = = 0 ifs/v = = 1 ifs/v = = 0 ifs/v xor n = = 1 ifs/v xor n = = 0 ifs/(v xor n) or z = = 1 ifs/(v xor n) or z = = 0 ifs/c or z = = 1 ifs/c or z = = 0 ri: temporary register * 2 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 MB91107/108 107 ? 32-bit normal macro branch instructions *1: call32 (1) if label32 C pc C 2 is between C0x800 and +0x7fe, instruction is generated as follows; call label12 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:32 #label32, ri call @ri *2: bra32 (1) if label32 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bra label9 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:32 #label32, ri jmp @ri *3: bcc32 (beq32 to bhi32) (1) if label32 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bcc label9 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; bxcc false xcc is a revolt condition of cc ldi:32 #label32, ri jmp @ri false: mnemonic operation remarks * call32 label32, ri next instruction address ? rp, label32 ? pc ri: temporary register * 1 * bra32 label32, ri * beq32 label32, ri * bne32 label32, ri * bc32 label32, ri * bnc32 label32, ri * bn32 label32, ri * bp32 label32, ri * bv32 label32, ri * bnv32 label32, ri * blt32 label32, ri * bge32 label32, ri * ble32 label32, ri * bgt32 label32, ri * bls32 label32, ri * bhi32 label32, ri label32 ? pc if (z = = 1) then label32 ? pc ifs/z = = 0 ifs/c = = 1 ifs/c = = 0 ifs/n = = 1 ifs/n = = 0 ifs/v = = 1 ifs/v = = 0 ifs/v xor n = = 1 ifs/v xor n = = 0 ifs/(v xor n) or z = = 1 ifs/(v xor n) or z = = 0 ifs/c or z = = 1 ifs/c or z = = 0 ri: temporary register * 2 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 MB91107/108 108 ? 32-bit delayed macro branch instructions *1: call32:d (1) if label32 C pc C 2 is between C0x800 and +0x7fe, instruction is generated as follows; call:d label12 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:32 #label32, ri call:d @ri *2: bra32:d (1) if label32 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bra:d label9 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:32 #label32, ri jmp:d @ri *3: bcc32:d (beq32:d to bhi32:d) (1) if label32 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bcc:d label9 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; bxcc false xcc is a revolt condition of cc ldi:32 #label32, ri jmp:d @ri false: mnemonic operation remarks * call32:d label32, ri next instruction address + 2 ? rp, label32 ? pc ri: temporary register * 1 * bra32:d label32, ri * beq32:d label32, ri * bne32:d label32, ri * bc32:d label32, ri * bnc32:d label32, ri * bn32:d label32, ri * bp32:d label32, ri * bv32:d label32, ri * bnv32:d label32, ri * blt32:d label32, ri * bge32:d label32, ri * ble32:d label32, ri * bgt32:d label32, ri * bls32:d label32, ri * bhi32:d label32, ri label32 ? pc if (z = = 1) then label32 ? pc ifs/z = = 0 ifs/c = = 1 ifs/c = = 0 ifs/n = = 1 ifs/n = = 0 ifs/v = = 1 ifs/v = = 0 ifs/v xor n = = 1 ifs/v xor n = = 0 ifs/(v xor n) or z = = 1 ifs/(v xor n) or z = = 0 ifs/c or z = = 1 ifs/c or z = = 0 ri: temporary register * 2 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 MB91107/108 109 n ordering information part number package remarks MB91107pfv mb91108pfv 120-pin plastic lqfp (fpt-120p-m21) MB91107/108 110 n package dimensions 120-pin plastic lqfp (fpt-120p-m21) dimensions in mm (inches) c 1998 fujitsu limited f120033s-2c-2 1 30 60 31 90 61 120 91 16.00?.10(.630?004)sq 18.00?.20(.709?008)sq 0.50(.020) 0.22?.05 (.009?002) m 0.08(.003) index .006 ?001 +.002 ?.03 +0.05 0.145 "a" 0.08(.003) lead no. .059 ?004 +.008 ?.10 +0.20 1.50 details of "a" part 0~8 (mounting height) 0.45/0.75 (.018/.030) 0.25(.010) (.004?002) 0.10?.05 (stand off) MB91107/108 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3347 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0101 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan. |
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